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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.9 2002/09/07 19:16:10 lampret
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// If SR[CY] implemented with OR1200_IMPL_ADDC enabled, l.add/l.addi also set SR[CY].
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//
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// Revision 1.8 2002/09/07 05:42:02 lampret
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// Revision 1.8 2002/09/07 05:42:02 lampret
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// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS.
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// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS.
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//
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//
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// Revision 1.7 2002/09/03 22:28:21 lampret
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// Revision 1.7 2002/09/03 22:28:21 lampret
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// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.
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// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.
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reg [width-1:0] shifted_rotated;
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reg [width-1:0] shifted_rotated;
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reg flagforw;
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reg flagforw;
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reg flagcomp;
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reg flagcomp;
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reg flag_we;
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reg flag_we;
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reg cy_we;
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reg cy_we;
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// synopsys translate_off
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`ifdef OR1200_SIM_ALU_DIV
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integer d1;
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integer d2;
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`endif
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// synopsys translate_on
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wire [width-1:0] comp_a;
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wire [width-1:0] comp_a;
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wire [width-1:0] comp_b;
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wire [width-1:0] comp_b;
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`ifdef OR1200_IMPL_ALU_COMP1
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`ifdef OR1200_IMPL_ALU_COMP1
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wire a_eq_b;
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wire a_eq_b;
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wire a_lt_b;
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wire a_lt_b;
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Line 214... |
end
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end
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else begin
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else begin
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result = b << 16;
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result = b << 16;
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end
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end
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end
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end
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`ifdef OR1200_IMPL_DIV
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`OR1200_ALUOP_DIV,
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`OR1200_ALUOP_DIVU,
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`endif
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`OR1200_ALUOP_MUL : begin
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`OR1200_ALUOP_MUL : begin
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result = mult_mac_result;
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result = mult_mac_result;
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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$display("%t: MUL operation: %h * %h = %h", $time, a, b, mult_mac_result);
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// synopsys translate_on
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`endif
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end
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// synopsys translate_off
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`ifdef OR1200_SIM_ALU_DIV
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`OR1200_ALUOP_DIV : begin
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d1 = a;
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d2 = b;
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$display("DIV operation: %d / %d = %d", d1, d2, d1/d2);
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if (d2)
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result = d1 / d2;
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else
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result = 32'h00000000;
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end
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`endif
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`ifdef OR1200_SIM_ALU_DIVU
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`OR1200_ALUOP_DIVU : begin
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if (b)
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result = a / b;
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else
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result = 32'h00000000;
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end
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end
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`endif
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// synopsys translate_on
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`ifdef OR1200_CASE_DEFAULT
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`ifdef OR1200_CASE_DEFAULT
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default: begin
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default: begin
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`else
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`else
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`OR1200_ALUOP_COMP, `OR1200_ALUOP_AND
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`OR1200_ALUOP_COMP, `OR1200_ALUOP_AND
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`endif
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`endif
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Line 266... |
end
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end
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//
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//
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// Generate SR[CY] write enable
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// Generate SR[CY] write enable
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//
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//
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always @(alu_op or cy_sum or cy_csum) begin
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always @(alu_op or cy_sum
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`ifdef OR1200_IMPL_ADDC
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or cy_csum
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`endif
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) begin
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casex (alu_op) // synopsys parallel_case
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casex (alu_op) // synopsys parallel_case
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`ifdef OR1200_IMPL_ADDC
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`ifdef OR1200_IMPL_ADDC
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`OR1200_ALUOP_ADD : begin
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`OR1200_ALUOP_ADD : begin
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cyforw = cy_sum;
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cyforw = cy_sum;
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cy_we = 1'b1;
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cy_we = 1'b1;
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