| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.9.4.2 2004/01/17 21:14:14 simons
|
|
// Errors fixed.
|
|
//
|
// Revision 1.9.4.1 2004/01/15 06:46:38 markom
|
// Revision 1.9.4.1 2004/01/15 06:46:38 markom
|
// interface to debug changed; no more opselect; stb-ack protocol
|
// interface to debug changed; no more opselect; stb-ack protocol
|
//
|
//
|
// Revision 1.9 2003/01/22 03:23:47 lampret
|
// Revision 1.9 2003/01/22 03:23:47 lampret
|
// Updated sensitivity list for trace buffer [only relevant for Xilinx FPGAs]
|
// Updated sensitivity list for trace buffer [only relevant for Xilinx FPGAs]
|
| Line 116... |
Line 119... |
du_read, du_write, du_except,
|
du_read, du_write, du_except,
|
spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
|
spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
|
|
|
// External Debug Interface
|
// External Debug Interface
|
dbg_stall_i, dbg_ewt_i, dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o,
|
dbg_stall_i, dbg_ewt_i, dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o,
|
dbg_stb_i, dbg_we_i, dbg_adr_i, dbg_dat_i, dbg_dat_o, dbg_ack_o,
|
dbg_stb_i, dbg_we_i, dbg_adr_i, dbg_dat_i, dbg_dat_o, dbg_ack_o
|
);
|
);
|
|
|
parameter dw = `OR1200_OPERAND_WIDTH;
|
parameter dw = `OR1200_OPERAND_WIDTH;
|
parameter aw = `OR1200_OPERAND_WIDTH;
|
parameter aw = `OR1200_OPERAND_WIDTH;
|
|
|
