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[/] [or1k/] [tags/] [asyst_3/] [or1200/] [rtl/] [verilog/] [or1200_ic_ram.v] - Diff between revs 504 and 1063

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Rev 504	Rev 1063
Line 42...	Line 42...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.1 2002/01/03 08:16:15 lampret`
	`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
	`//`
`// Revision 1.9 2001/10/21 17:57:16 lampret`	`// Revision 1.9 2001/10/21 17:57:16 lampret`
`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`	`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
`//`	`//`
`// Revision 1.8 2001/10/14 13:12:09 lampret`	`// Revision 1.8 2001/10/14 13:12:09 lampret`
`// MP3 version.`	`// MP3 version.`
Line 71...	Line 74...

`module or1200_ic_ram(`	`module or1200_ic_ram(`
`// Clock and reset`	`// Clock and reset`
`clk, rst,`	`clk, rst,`

	`ifdef OR1200_BIST
	`// RAM BIST`
	`scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,`
	`endif

`// Internal i/f`	`// Internal i/f`
`addr, en, we, datain, dataout`	`addr, en, we, datain, dataout`
`);`	`);`

parameter dw = `OR1200_OPERAND_WIDTH;	parameter dw = `OR1200_OPERAND_WIDTH;
Line 89...	Line 97...
`input en;`	`input en;`
`input [3:0] we;`	`input [3:0] we;`
`input [dw-1:0] datain;`	`input [dw-1:0] datain;`
`output [dw-1:0] dataout;`	`output [dw-1:0] dataout;`

	`ifdef OR1200_BIST
	`//`
	`// RAM BIST`
	`//`
	`input scanb_rst,`
	`scanb_si,`
	`scanb_en,`
	`scanb_clk;`
	`output scanb_so;`
	`endif

`ifdef OR1200_NO_IC	`ifdef OR1200_NO_IC

`//`	`//`
`// Insn cache not implemented`	`// Insn cache not implemented`
`//`	`//`
`assign dataout = {dw{1'b0}};`	`assign dataout = {dw{1'b0}};`
	`ifdef OR1200_BIST
	`assign scanb_so = scanb_si;`
	`endif

`else	`else

`//`	`//`
`// Instantiation of IC RAM block`	`// Instantiation of IC RAM block`
Line 107...	Line 129...
`or1200_spram_1024x32 ic_ram0(`	`or1200_spram_1024x32 ic_ram0(`
`endif	`endif
`ifdef OR1200_IC_1W_8KB	`ifdef OR1200_IC_1W_8KB
`or1200_spram_2048x32 ic_ram0(`	`or1200_spram_2048x32 ic_ram0(`
`endif	`endif
	`ifdef OR1200_BIST
	`// RAM BIST`
	`.scanb_rst(scanb_rst),`
	`.scanb_si(scanb_si),`
	`.scanb_so(scanb_so),`
	`.scanb_en(scanb_en),`
	`.scanb_clk(scanb_clk),`
	`endif
`.clk(clk),`	`.clk(clk),`
`.rst(rst),`	`.rst(rst),`
`.ce(en),`	`.ce(en),`
`.we(we[0]),`	`.we(we[0]),`
`.oe(1'b1),`	`.oe(1'b1),`

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[/] [or1k/] [tags/] [asyst_3/] [or1200/] [rtl/] [verilog/] [or1200_ic_ram.v] - Diff between revs 504 and 1063