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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.4 2002/02/01 19:56:54 lampret
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// Fixed combinational loops.
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//
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// Revision 1.3 2002/01/28 01:16:00 lampret
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// Revision 1.3 2002/01/28 01:16:00 lampret
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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//
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//
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// Revision 1.2 2002/01/14 06:18:22 lampret
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// Revision 1.2 2002/01/14 06:18:22 lampret
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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Line 88... |
module or1200_immu_top(
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module or1200_immu_top(
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// Rst and clk
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// Rst and clk
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clk, rst,
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clk, rst,
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// CPU i/f
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// CPU i/f
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ic_en, immu_en, supv, icpu_adr_i, icpu_cyc_i, icpu_stb_i,
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ic_en, immu_en, supv, icpu_adr_i, icpu_cycstb_i,
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icpu_adr_o, icpu_tag_o, icpu_rty_o, icpu_err_o,
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icpu_adr_o, icpu_tag_o, icpu_rty_o, icpu_err_o,
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// SPR access
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// SPR access
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spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
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spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
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// IC i/f
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// IC i/f
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icimmu_rty_i, icimmu_err_i, icimmu_tag_i, icimmu_adr_o, icimmu_cyc_o, icimmu_stb_o, icimmu_ci_o
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icimmu_rty_i, icimmu_err_i, icimmu_tag_i, icimmu_adr_o, icimmu_cycstb_o, icimmu_ci_o
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);
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);
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parameter dw = `OR1200_OPERAND_WIDTH;
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parameter dw = `OR1200_OPERAND_WIDTH;
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parameter aw = `OR1200_OPERAND_WIDTH;
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parameter aw = `OR1200_OPERAND_WIDTH;
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Line 118... |
//
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//
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input ic_en;
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input ic_en;
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input immu_en;
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input immu_en;
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input supv;
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input supv;
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input [aw-1:0] icpu_adr_i;
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input [aw-1:0] icpu_adr_i;
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input icpu_cyc_i;
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input icpu_cycstb_i;
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input icpu_stb_i;
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output [aw-1:0] icpu_adr_o;
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output [aw-1:0] icpu_adr_o;
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output [3:0] icpu_tag_o;
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output [3:0] icpu_tag_o;
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output icpu_rty_o;
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output icpu_rty_o;
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output icpu_err_o;
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output icpu_err_o;
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Line 140... |
//
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//
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input icimmu_rty_i;
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input icimmu_rty_i;
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input icimmu_err_i;
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input icimmu_err_i;
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input [3:0] icimmu_tag_i;
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input [3:0] icimmu_tag_i;
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output [aw-1:0] icimmu_adr_o;
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output [aw-1:0] icimmu_adr_o;
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output icimmu_cyc_o;
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output icimmu_cycstb_o;
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output icimmu_stb_o;
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output icimmu_ci_o;
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output icimmu_ci_o;
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//
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//
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// Internal wires and regs
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// Internal wires and regs
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//
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//
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Line 159... |
wire itlb_done;
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wire itlb_done;
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wire fault;
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wire fault;
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wire miss;
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wire miss;
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reg [31:0] icpu_adr_o;
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reg [31:0] icpu_adr_o;
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reg itlb_en_r;
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reg itlb_en_r;
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reg [31:`OR1200_IMMU_PS] icpu_vpn_r;
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//
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//
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// Implemented bits inside match and translate registers
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// Implemented bits inside match and translate registers
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//
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//
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// itlbwYmrX: vpn 31-10 v 0
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// itlbwYmrX: vpn 31-10 v 0
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Line 195... |
// Put all outputs in inactive state
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// Put all outputs in inactive state
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//
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//
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assign spr_dat_o = 32'h00000000;
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assign spr_dat_o = 32'h00000000;
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assign icimmu_adr_o = icpu_adr_i;
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assign icimmu_adr_o = icpu_adr_i;
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assign icpu_tag_o = icimmu_tag_i;
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assign icpu_tag_o = icimmu_tag_i;
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assign icimmu_cyc_o = icpu_cyc_i;
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assign icimmu_cycstb_o = icpu_cycstb_i;
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assign icimmu_stb_o = icpu_stb_i;
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assign icpu_rty_o = icimmu_rty_i;
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assign icpu_rty_o = icimmu_rty_i;
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assign icpu_err_o = icimmu_err_i;
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assign icpu_err_o = icimmu_err_i;
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assign icimmu_ci_o = icpu_adr_i[31];
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assign icimmu_ci_o = `OR1200_IMMU_CI;
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`else
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`else
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//
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//
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// ITLB SPR access
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// ITLB SPR access
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itlb_en_r <= #1 itlb_en;
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itlb_en_r <= #1 itlb_en;
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//
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//
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// Assert itlb_done one clock cycle after new address is first presented and tlb is enabled.
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// Assert itlb_done one clock cycle after new address is first presented and tlb is enabled.
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//
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//
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assign itlb_done = (icpu_adr_i == icpu_adr_o) & itlb_en_r;
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// assign itlb_done = (icpu_adr_i == icpu_adr_o) & itlb_en_r;
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assign itlb_done = itlb_en_r;
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//
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//
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// Cut transfer if something goes wrong with translation. If IC is disabled,
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// Cut transfer if something goes wrong with translation. If IC is disabled,
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// use delayed signals.
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// use delayed signals.
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//
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//
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assign icimmu_cyc_o = (!ic_en & immu_en) ? ~(miss | fault) & itlb_done & icpu_cyc_i : (miss | fault) ? 1'b0 : icpu_cyc_i;
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assign icimmu_cycstb_o = (!ic_en & immu_en) ? ~(miss | fault) & icpu_cycstb_i : (miss | fault) ? 1'b0 : icpu_cycstb_i;
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assign icimmu_stb_o = (!ic_en & immu_en) ? ~(miss | fault) & itlb_done & icpu_stb_i : (miss | fault) ? 1'b0 : icpu_stb_i;
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//
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//
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// Cache Inhibit
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// Cache Inhibit
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//
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//
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assign icimmu_ci_o = immu_en ? itlb_done & itlb_ci : icpu_adr_i[31];
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assign icimmu_ci_o = immu_en ? itlb_done & itlb_ci : `OR1200_IMMU_CI;
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//
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// Register icpu_adr_i's VPN for use when IMMU is not enabled but PPN is expected to come
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// one clock cycle after offset part.
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//
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always @(posedge clk or posedge rst)
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if (rst)
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icpu_vpn_r <= #1 {31-`OR1200_IMMU_PS{1'b0}};
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else
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icpu_vpn_r <= #1 icpu_adr_i[31:`OR1200_IMMU_PS];
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//
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//
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// Physical address is either translated virtual address or
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// Physical address is either translated virtual address or
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// simply equal when IMMU is disabled
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// simply equal when IMMU is disabled
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//
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//
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assign icimmu_adr_o = immu_en ? {itlb_ppn, icpu_adr_i[`OR1200_IMMU_PS-1:0]} : icpu_adr_i;
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assign icimmu_adr_o = immu_en ? {itlb_ppn, icpu_adr_i[`OR1200_IMMU_PS-1:0]} : {icpu_vpn_r, icpu_adr_i[`OR1200_IMMU_PS-1:0]};
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//
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//
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// Output to SPRS unit
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// Output to SPRS unit
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//
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//
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assign spr_dat_o = itlb_spr_access ? itlb_dat_o : 32'h00000000;
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assign spr_dat_o = itlb_spr_access ? itlb_dat_o : 32'h00000000;
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Line 294... |
assign miss = itlb_done & !itlb_hit;
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assign miss = itlb_done & !itlb_hit;
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//
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//
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// ITLB Enable
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// ITLB Enable
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//
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//
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assign itlb_en = immu_en & icpu_cyc_i & icpu_stb_i;
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assign itlb_en = immu_en & icpu_cycstb_i;
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//
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//
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// Instantiation of ITLB
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// Instantiation of ITLB
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//
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//
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or1200_immu_tlb or1200_immu_tlb(
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or1200_immu_tlb or1200_immu_tlb(
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