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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2002/03/28 19:14:10 lampret
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// Changed define name from OR1200_MEM2REG_FAST to OR1200_IMPL_MEM2REG2
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//
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// Revision 1.2 2002/01/14 06:18:22 lampret
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// Revision 1.2 2002/01/14 06:18:22 lampret
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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//
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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Line 203... |
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//
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//
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// Byte 0
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// Byte 0
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//
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//
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always @(sel_byte0 or memdata) begin
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always @(sel_byte0 or memdata) begin
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`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
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case(sel_byte0) // synopsys full_case parallel_case infer_mux
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case(sel_byte0) // synopsys full_case parallel_case infer_mux
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`else
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case(sel_byte0) // synopsys full_case parallel_case
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`endif
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`OR1200_M2R_BYTE0: begin
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`OR1200_M2R_BYTE0: begin
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regdata_ll = memdata[7:0];
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regdata_ll = memdata[7:0];
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end
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end
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`OR1200_M2R_BYTE1: begin
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`OR1200_M2R_BYTE1: begin
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regdata_ll = memdata[15:8];
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regdata_ll = memdata[15:8];
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Line 227... |
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//
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//
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// Byte 1
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// Byte 1
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//
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//
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always @(sel_byte1 or memdata) begin
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always @(sel_byte1 or memdata) begin
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`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
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case(sel_byte1) // synopsys full_case parallel_case infer_mux
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case(sel_byte1) // synopsys full_case parallel_case infer_mux
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`else
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case(sel_byte1) // synopsys full_case parallel_case
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`endif
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`OR1200_M2R_ZERO: begin
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`OR1200_M2R_ZERO: begin
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regdata_lh = 8'h00;
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regdata_lh = 8'h00;
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end
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end
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`OR1200_M2R_BYTE1: begin
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`OR1200_M2R_BYTE1: begin
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regdata_lh = memdata[15:8];
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regdata_lh = memdata[15:8];
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Line 260... |
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//
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//
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// Byte 2
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// Byte 2
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//
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//
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always @(sel_byte2 or memdata) begin
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always @(sel_byte2 or memdata) begin
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`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
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case(sel_byte2) // synopsys full_case parallel_case infer_mux
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case(sel_byte2) // synopsys full_case parallel_case infer_mux
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`else
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case(sel_byte2) // synopsys full_case parallel_case
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`endif
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`OR1200_M2R_ZERO: begin
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`OR1200_M2R_ZERO: begin
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regdata_hl = 8'h00;
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regdata_hl = 8'h00;
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end
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end
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`OR1200_M2R_BYTE2: begin
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`OR1200_M2R_BYTE2: begin
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regdata_hl = memdata[23:16];
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regdata_hl = memdata[23:16];
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Line 290... |
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//
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//
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// Byte 3
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// Byte 3
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//
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//
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always @(sel_byte3 or memdata) begin
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always @(sel_byte3 or memdata) begin
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`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
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case(sel_byte3) // synopsys full_case parallel_case infer_mux
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case(sel_byte3) // synopsys full_case parallel_case infer_mux
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`else
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case(sel_byte3) // synopsys full_case parallel_case
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`endif
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`OR1200_M2R_ZERO: begin
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`OR1200_M2R_ZERO: begin
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regdata_hh = 8'h00;
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regdata_hh = 8'h00;
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end
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end
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`OR1200_M2R_BYTE3: begin
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`OR1200_M2R_BYTE3: begin
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regdata_hh = memdata[31:24];
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regdata_hh = memdata[31:24];
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Line 319... |
end
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end
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`else
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`else
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//
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//
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// Slow implementation of mem2reg
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// Straightforward implementation of mem2reg
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//
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//
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reg [width-1:0] regdata;
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reg [width-1:0] regdata;
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reg [width-1:0] aligned;
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reg [width-1:0] aligned;
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//
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//
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// Alignment
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// Alignment
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//
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//
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always @(addr or memdata) begin
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always @(addr or memdata) begin
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`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
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case(addr) // synopsys infer_mux
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case(addr) // synopsys infer_mux
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`else
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case(addr) // synopsys full_case parallel_case
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`endif
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2'b00:
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2'b00:
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aligned = memdata;
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aligned = memdata;
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2'b01:
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2'b01:
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aligned = {memdata[23:0], 8'b0};
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aligned = {memdata[23:0], 8'b0};
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2'b10:
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2'b10:
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Line 349... |
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//
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//
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// Bytes
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// Bytes
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//
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//
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always @(lsu_op or aligned) begin
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always @(lsu_op or aligned) begin
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`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
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case(lsu_op) // synopsys infer_mux
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case(lsu_op) // synopsys infer_mux
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`else
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case(lsu_op) // synopsys parallel_case
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`endif
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`OR1200_LSUOP_LBZ: begin
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`OR1200_LSUOP_LBZ: begin
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regdata[7:0] = aligned[31:24];
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regdata[7:0] = aligned[31:24];
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regdata[31:8] = 24'b0;
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regdata[31:8] = 24'b0;
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end
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end
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`OR1200_LSUOP_LBS: begin
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`OR1200_LSUOP_LBS: begin
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