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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2002/06/08 16:23:30 lampret
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// Generic flip-flop based memory macro for register file.
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//
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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if (rst) begin
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if (rst) begin
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mem <= #1 1024'h0;
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mem <= #1 1024'h0;
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end
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end
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else if (ce_w & we_w)
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else if (ce_w & we_w)
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case (addr_w) // synopsys parallel_case full_case
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case (addr_w) // synopsys parallel_case
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5'd00: mem[32*0+31:32*0] <= #1 di_w;
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5'd00: mem[32*0+31:32*0] <= #1 di_w;
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5'd01: mem[32*1+31:32*1] <= #1 di_w;
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5'd01: mem[32*1+31:32*1] <= #1 di_w;
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5'd02: mem[32*2+31:32*2] <= #1 di_w;
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5'd02: mem[32*2+31:32*2] <= #1 di_w;
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5'd03: mem[32*3+31:32*3] <= #1 di_w;
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5'd03: mem[32*3+31:32*3] <= #1 di_w;
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5'd04: mem[32*4+31:32*4] <= #1 di_w;
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5'd04: mem[32*4+31:32*4] <= #1 di_w;
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5'd26: mem[32*26+31:32*26] <= #1 di_w;
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5'd26: mem[32*26+31:32*26] <= #1 di_w;
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5'd27: mem[32*27+31:32*27] <= #1 di_w;
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5'd27: mem[32*27+31:32*27] <= #1 di_w;
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5'd28: mem[32*28+31:32*28] <= #1 di_w;
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5'd28: mem[32*28+31:32*28] <= #1 di_w;
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5'd29: mem[32*29+31:32*29] <= #1 di_w;
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5'd29: mem[32*29+31:32*29] <= #1 di_w;
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5'd30: mem[32*30+31:32*30] <= #1 di_w;
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5'd30: mem[32*30+31:32*30] <= #1 di_w;
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5'd31: mem[32*31+31:32*31] <= #1 di_w;
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default: mem[32*31+31:32*31] <= #1 di_w;
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endcase
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endcase
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//
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//
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// Read port A
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// Read port A
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//
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//
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Line 163... |
end
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end
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else if (ce_a)
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else if (ce_a)
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intaddr_a <= #1 addr_a;
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intaddr_a <= #1 addr_a;
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always @(mem or intaddr_a)
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always @(mem or intaddr_a)
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case (intaddr_a) // synopsys parallel_case full_case
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case (intaddr_a) // synopsys parallel_case
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5'd00: do_a = mem[32*0+31:32*0];
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5'd00: do_a = mem[32*0+31:32*0];
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5'd01: do_a = mem[32*1+31:32*1];
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5'd01: do_a = mem[32*1+31:32*1];
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5'd02: do_a = mem[32*2+31:32*2];
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5'd02: do_a = mem[32*2+31:32*2];
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5'd03: do_a = mem[32*3+31:32*3];
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5'd03: do_a = mem[32*3+31:32*3];
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5'd04: do_a = mem[32*4+31:32*4];
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5'd04: do_a = mem[32*4+31:32*4];
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5'd26: do_a = mem[32*26+31:32*26];
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5'd26: do_a = mem[32*26+31:32*26];
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5'd27: do_a = mem[32*27+31:32*27];
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5'd27: do_a = mem[32*27+31:32*27];
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5'd28: do_a = mem[32*28+31:32*28];
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5'd28: do_a = mem[32*28+31:32*28];
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5'd29: do_a = mem[32*29+31:32*29];
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5'd29: do_a = mem[32*29+31:32*29];
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5'd30: do_a = mem[32*30+31:32*30];
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5'd30: do_a = mem[32*30+31:32*30];
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5'd31: do_a = mem[32*31+31:32*31];
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default: do_a = mem[32*31+31:32*31];
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endcase
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endcase
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//
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//
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// Read port B
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// Read port B
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//
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//
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Line 209... |
end
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end
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else if (ce_b)
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else if (ce_b)
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intaddr_b <= #1 addr_b;
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intaddr_b <= #1 addr_b;
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always @(mem or intaddr_b)
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always @(mem or intaddr_b)
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case (intaddr_b) // synopsys parallel_case full_case
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case (intaddr_b) // synopsys parallel_case
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5'd00: do_b = mem[32*0+31:32*0];
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5'd00: do_b = mem[32*0+31:32*0];
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5'd01: do_b = mem[32*1+31:32*1];
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5'd01: do_b = mem[32*1+31:32*1];
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5'd02: do_b = mem[32*2+31:32*2];
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5'd02: do_b = mem[32*2+31:32*2];
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5'd03: do_b = mem[32*3+31:32*3];
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5'd03: do_b = mem[32*3+31:32*3];
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5'd04: do_b = mem[32*4+31:32*4];
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5'd04: do_b = mem[32*4+31:32*4];
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5'd26: do_b = mem[32*26+31:32*26];
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5'd26: do_b = mem[32*26+31:32*26];
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5'd27: do_b = mem[32*27+31:32*27];
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5'd27: do_b = mem[32*27+31:32*27];
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5'd28: do_b = mem[32*28+31:32*28];
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5'd28: do_b = mem[32*28+31:32*28];
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5'd29: do_b = mem[32*29+31:32*29];
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5'd29: do_b = mem[32*29+31:32*29];
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5'd30: do_b = mem[32*30+31:32*30];
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5'd30: do_b = mem[32*30+31:32*30];
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5'd31: do_b = mem[32*31+31:32*31];
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default: do_b = mem[32*31+31:32*31];
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endcase
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endcase
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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