| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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// Revision 1.10 2001/11/13 10:00:49 lampret
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// Revision 1.10 2001/11/13 10:00:49 lampret
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// Fixed tick timer interrupt reporting by using TTCR[IP] bit.
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// Fixed tick timer interrupt reporting by using TTCR[IP] bit.
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//
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//
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// Revision 1.9 2001/11/10 03:43:57 lampret
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// Revision 1.9 2001/11/10 03:43:57 lampret
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// Fixed exceptions.
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// Fixed exceptions.
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| Line 72... |
Line 75... |
// synopsys translate_on
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// synopsys translate_on
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`include "or1200_defines.v"
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`include "or1200_defines.v"
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module or1200_tt(
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module or1200_tt(
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// RISC Internal Interface
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// RISC Internal Interface
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clk, rst, spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
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clk, rst, du_stall,
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spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
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int
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int
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);
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);
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//
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//
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// RISC Internal Interface
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// RISC Internal Interface
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//
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//
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input clk; // Clock
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input clk; // Clock
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input rst; // Reset
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input rst; // Reset
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input du_stall; // DU stall
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input spr_cs; // SPR CS
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input spr_cs; // SPR CS
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input spr_write; // SPR Write
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input spr_write; // SPR Write
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input [31:0] spr_addr; // SPR Address
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input [31:0] spr_addr; // SPR Address
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input [31:0] spr_dat_i; // SPR Write Data
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input [31:0] spr_dat_i; // SPR Write Data
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output [31:0] spr_dat_o; // SPR Read Data
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output [31:0] spr_dat_o; // SPR Read Data
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| Line 179... |
Line 184... |
// Restart when match and TTMR[M]==0x1 or when rst is asserted
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// Restart when match and TTMR[M]==0x1 or when rst is asserted
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//
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//
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assign restart = (match && (ttmr[`OR1200_TT_TTMR_M] == 2'b01) || rst) ? 1'b1 : 1'b0;
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assign restart = (match && (ttmr[`OR1200_TT_TTMR_M] == 2'b01) || rst) ? 1'b1 : 1'b0;
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//
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//
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// Stop when match and TTMR[M]==0x2 or when TTMR[M]==0x0
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// Stop when match and TTMR[M]==0x2 or when TTMR[M]==0x0 or when RISC is stalled by debug unit
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//
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//
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assign stop = (match && (ttmr[`OR1200_TT_TTMR_M] == 2'b10) || (ttmr[`OR1200_TT_TTMR_M] == 2'b00)) ? 1'b1 : 1'b0;
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assign stop = match & (ttmr[`OR1200_TT_TTMR_M] == 2'b10) | (ttmr[`OR1200_TT_TTMR_M] == 2'b00) | du_stall;
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//
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//
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// Generate an interrupt request
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// Generate an interrupt request
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//
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//
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assign int = ttmr[`OR1200_TT_TTMR_IP];
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assign int = ttmr[`OR1200_TT_TTMR_IP];
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