OpenCores

URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [before_ORP/] [uclinux/] [uClinux-2.0.x/] [sim.cfg] - Diff between revs 531 and 581

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 531	Rev 581
Line 108...	Line 108...
`ce = 0`	`ce = 0`
`baseaddr = 0x00000000`	`baseaddr = 0x00000000`
`size = 0x00800000`	`size = 0x00800000`
`delayr = 1`	`delayr = 1`
`delayw = 2`	`delayw = 2`
	`log = "ram.log"`
`enddevice`	`enddevice`

`device 1`	`device 1`
`name = "FLASH"`	`name = "FLASH"`
`ce = 1`	`ce = 1`
`baseaddr = 0x40000000`	`baseaddr = 0x04000000`
`size = 0x00200000`	`size = 0x00200000`
`delayr = 10`	`delayr = 10`
`delayw = -1`	`delayw = -1`
	`log = "flash.log"`
`enddevice`	`enddevice`
`end`	`end`

`/* IMMU SECTION`	`/* IMMU SECTION`

Line 446...	Line 448...
`section uart`	`section uart`
`enabled = 1`	`enabled = 1`
`nuarts = 1`	`nuarts = 1`

`device 0`	`device 0`
`baseaddr = 0x80000000`	`baseaddr = 0x9c000000`
`irq = 2`	`irq = 2`
`rxfile = "/tmp/uart0.rx"`	`rxfile = "/tmp/uart0.rx"`
`txfile = "/tmp/uart0.tx"`	`txfile = "/tmp/uart0.tx"`
`jitter = -1 /* async behaviour */`	`jitter = -1 /* async behaviour */`
`16550 = 1`	`16550 = 1`

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.