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Line 27... |
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extern int cont_run;
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extern int cont_run;
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extern struct iqueue_entry iqueue[20];
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extern struct iqueue_entry iqueue[20];
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extern unsigned long pc;
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extern unsigned long pc;
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extern unsigned long pcnext;
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extern unsigned long pcnext;
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extern unsigned long pc_phy;
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extern struct iqueue_entry iqueue[];
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extern struct iqueue_entry iqueue[];
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extern int delay_insn;
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extern int delay_insn;
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int cycle_delay = 0; /* Added by CZ 27/05/01 */
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/* Handle OR1K exceptions. */
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/* Handle OR1K exceptions. */
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void except_handle(int except, unsigned long ea)
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void except_handle(int except, unsigned long ea)
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{
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{
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unsigned long pc_saved;
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unsigned long pc_saved;
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Line 78... |
mtspr(SPR_SR, mfspr(SPR_SR) & ~(SPR_SR_IME));
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mtspr(SPR_SR, mfspr(SPR_SR) & ~(SPR_SR_IME));
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mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_SUPV); /* SUPV mode */
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mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_SUPV); /* SUPV mode */
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mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_EXR); /* Disable except. */
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mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_EXR); /* Disable except. */
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pc = (unsigned long)except;
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pc = (unsigned long)except;
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pcnext = (unsigned long)except;
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/* MM: We do pc update after the execute (in the simulator), so we
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decrease it by 4 so that next instruction points to first exception
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instruction. */
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if (except == EXCEPT_SYSCALL)
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pc -= 4;
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pcnext = pc+4;
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/* Added by CZ 27/05/01 */
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pc_phy = pc;
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cycle_delay = 7; /* An exception stalls the CPU 7 clock cycles */
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#endif
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#endif
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}
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}
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