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Line 23... |
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#include "abstract.h"
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#include "abstract.h"
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#include "except.h"
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#include "except.h"
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#include "sprs.h"
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#include "sprs.h"
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static void except_handle_backend(int,unsigned long,unsigned long);
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extern int cont_run;
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extern int cont_run;
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extern struct iqueue_entry iqueue[20];
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extern struct iqueue_entry iqueue[20];
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extern unsigned long pc;
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extern unsigned long pc;
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extern unsigned long pcnext;
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extern unsigned long pcnext;
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extern unsigned long pc_phy;
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extern unsigned long pc_phy;
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extern struct iqueue_entry iqueue[];
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extern struct iqueue_entry iqueue[];
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extern int delay_insn;
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extern int delay_insn;
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int cycle_delay = 0; /* Added by CZ 27/05/01 */
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int cycle_delay = 0; /* Added by CZ 27/05/01 */
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static struct {
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int valid;
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int type;
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unsigned long address;
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unsigned long saved;
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} pending;
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void ClearPendingException()
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{
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if(pending.valid && pending.type != EXCEPT_RESET)
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{
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pending.valid = 0;
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pending.type = 0;
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pending.address = 0;
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pending.saved = 0;
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}
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}
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/* The delayed_pc and delayed_pcnext are fields which hold
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the original value of the PC across breakpoint exceptions
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in the case of a development interface. Due to an implementation
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issues, DIR injected instructions can modify these values
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when in fact they should not. So we save and restore them
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later on. */
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static unsigned long delayed_pc = 0;
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static unsigned long delayed_pcnext = 0;
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static int delayed_pc_valid = 0;
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void PrepareExceptionPC(unsigned long t_pc,unsigned long t_pcnext)
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{
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/* If a real exception occurred which has stalled
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the CPU, we are expecting to halt before the end
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of the instruction. Otherwise, if it is a single
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step that has caused the halt, we are expected to
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complete the entire instruction and stop after
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it is finished. */
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if(pending.valid)
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{
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delayed_pc = t_pc;
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delayed_pcnext = t_pcnext;
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delayed_pc_valid = 1;
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}
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else
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_execute_update_pc(t_pc,t_pcnext);
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}
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void PrepareException()
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{
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if(delayed_pc_valid)
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{
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pc = delayed_pc;
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pcnext = delayed_pcnext;
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pc_phy = simulate_ic_mmu_fetch(pc);
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if ((pc_phy < MEMORY_START) || (pc_phy > MEMORY_START + MEMORY_LEN))
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except_handle(EXCEPT_BUSERR, pc);
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delayed_pc_valid = delayed_pc = delayed_pcnext = 0;
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}
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if(pending.valid)
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except_handle_backend(pending.type,pending.address,pending.saved);
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}
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/* Handle OR1K exceptions. */
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/* Handle OR1K exceptions. */
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void except_handle(int except, unsigned long ea)
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void except_handle(int except, unsigned long ea)
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{
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{
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unsigned long pc_saved;
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printf("Exception 0x%x (%s): ", except, EXCEPT_NAME(except));
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printf("Exception 0x%x (%s): ", except, EXCEPT_NAME(except));
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printf("Iqueue[0].insn_addr: 0x%x Eff ADDR: 0x%x\n", iqueue[0].insn_addr, ea);
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printf("Iqueue[0].insn_addr: 0x%x Eff ADDR: 0x%x\n", iqueue[0].insn_addr, ea);
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printf(" pc: 0x%x pcnext: 0x%x\n", pc, pcnext);
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printf(" pc: 0x%x pcnext: 0x%x\n", pc, pcnext);
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pending.valid = 1;
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pending.type = except;
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pending.address = ea;
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pending.saved = pc;
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if(DebugCheckException(except))
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{
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pending.valid = 0;
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pending.type = 0;
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pending.address = 0;
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pending.saved = 0;
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}
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cycle_delay = 0; /* An exception stalls the CPU 0 clock cycles */
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}
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static void except_handle_backend(int except, unsigned long ea, unsigned long pc_saved)
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{
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pending.valid = 0;
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pending.type = 0;
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pending.address = 0;
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pending.saved = 0;
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#if ONLY_VIRTUAL_MACHINE
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#if ONLY_VIRTUAL_MACHINE
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printf("WARNING: No exception processing while ONLY_VIRTUAL_MACHINE is defined.\n");
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printf("WARNING: No exception processing while ONLY_VIRTUAL_MACHINE is defined.\n");
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cont_run = 0;
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cont_run = 0;
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#else
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#else
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| Line 79... |
Line 165... |
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mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_SUPV); /* SUPV mode */
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mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_SUPV); /* SUPV mode */
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mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_EXR); /* Disable except. */
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mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_EXR); /* Disable except. */
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pc = (unsigned long)except;
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pc = (unsigned long)except;
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/* This has been removed. All exceptions (not just SYSCALL) suffer
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from the same problem. The solution is to continue just like
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the pipeline would, and issue the exception on the next
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clock cycle. We assume now that this function is being called
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->BEFORE<- the instruction fetch and after the previous update
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which always yields the correct behavior. This has the added
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advantage that a debugger can prevent an exception from
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taking place by resetting the pc. */
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#if 0
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/* MM: We do pc update after the execute (in the simulator), so we
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/* MM: We do pc update after the execute (in the simulator), so we
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decrease it by 4 so that next instruction points to first exception
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decrease it by 4 so that next instruction points to first exception
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instruction. */
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instruction. */
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if (except == EXCEPT_SYSCALL)
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if (except == EXCEPT_SYSCALL)
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pc -= 4;
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pc -= 4;
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#endif
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pcnext = pc+4;
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pcnext = pc+4;
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/* Added by CZ 27/05/01 */
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/* Added by CZ 27/05/01 */
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pc_phy = pc;
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pc_phy = pc; /* An exception always turns off the MMU, so
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cycle_delay = 7; /* An exception stalls the CPU 7 clock cycles */
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pc is always pc_phy */
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#endif
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#endif
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}
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}
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