OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [nog_patch_34/] [or1ksim/] [cpu/] [or32/] [execute.c] - Diff between revs 677 and 678

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 677 Rev 678
Line 536... Line 536...
{
{
  unsigned long i = iqueue[0].insn_addr;
  unsigned long i = iqueue[0].insn_addr;
 
 
  if (i == 0xffffffff) return;
  if (i == 0xffffffff) return;
  if (config.sim.exe_log_marker && instructions % config.sim.exe_log_marker == 0) {
  if (config.sim.exe_log_marker && instructions % config.sim.exe_log_marker == 0) {
    fprintf (runtime.sim.fexe_log, "--------------------- %8i instruction ---------------------\n");
    fprintf (runtime.sim.fexe_log, "--------------------- %8i instruction ---------------------\n", instructions);
  }
  }
  if (config.sim.exe_log_start <= instructions && (config.sim.exe_log_end <= 0 || instructions <= config.sim.exe_log_end)) {
  if (config.sim.exe_log_start <= instructions && (config.sim.exe_log_end <= 0 || instructions <= config.sim.exe_log_end)) {
    switch (config.sim.exe_log_type) {
    switch (config.sim.exe_log_type) {
    case EXE_LOG_HARDWARE:
    case EXE_LOG_HARDWARE:
      fprintf (runtime.sim.fexe_log, "\nEXECUTED(): %.8lx:  ", i);
      fprintf (runtime.sim.fexe_log, "\nEXECUTED(): %.8lx:  ", i);
Line 574... Line 574...
        }
        }
 
 
        if (labels) fprintf (runtime.sim.fexe_log, "\n");
        if (labels) fprintf (runtime.sim.fexe_log, "\n");
 
 
        if (config.sim.exe_log_type == EXE_LOG_SOFTWARE) {
        if (config.sim.exe_log_type == EXE_LOG_SOFTWARE) {
          int i, nregs = 0;
          int i;
          for (i = 0; i < 3; i++)
          for (i = 0; i < num_op; i++)
            if (op[i + MAX_OPERANDS] & OPTYPE_DIS) {
            if (op[i + MAX_OPERANDS] & OPTYPE_DIS) {
              fprintf (runtime.sim.fexe_log, "EA =%08x ", op[i]);
              fprintf (runtime.sim.fexe_log, "EA =%08x ", op[i]);
              nregs++;
 
            } else if ((op[i + MAX_OPERANDS] & OPTYPE_REG) && op[i]) {
            } else if ((op[i + MAX_OPERANDS] & OPTYPE_REG) && op[i]) {
              fprintf (runtime.sim.fexe_log, "r%-2i=%08x ", op[i], evalsim_reg32 (op[i]));
              fprintf (runtime.sim.fexe_log, "r%-2i=%08x ", op[i], evalsim_reg32 (op[i]));
              nregs++;
 
            } else
            } else
            fprintf (runtime.sim.fexe_log, "             ");
            fprintf (runtime.sim.fexe_log, "             ");
 
          for (; i < 3; i++)
 
            fprintf (runtime.sim.fexe_log, "             ");
        }
        }
 
 
        fprintf (runtime.sim.fexe_log, "%.8lx ", i);
        fprintf (runtime.sim.fexe_log, "%.8lx ", i);
        if (index >= 0) {
        if (index >= 0) {
          extern char *disassembled;
          extern char *disassembled;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.