OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [nog_patch_34/] [or1ksim/] [cuc/] [verilog.c] - Diff between revs 1048 and 1059

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 1048 Rev 1059
Line 775... Line 775...
  GEN ("assign i_selected = {\n");
  GEN ("assign i_selected = {\n");
  for (i = 0; i < nrf; i++)
  for (i = 0; i < nrf; i++)
    GEN ("    cuc_adr_i[15:6] == %i%s\n", i, i < nrf - 1 ? "," : "};");
    GEN ("    cuc_adr_i[15:6] == %i%s\n", i, i < nrf - 1 ? "," : "};");
 
 
  GEN ("assign i_first_reg = {\n");
  GEN ("assign i_first_reg = {\n");
  for (i = 0; i < nrf; i++) {
  for (i = 0; i < nfuncs; i++) if (f[i]) {
    for (j = 0; j <= MAX_REGS; j++) if (f[i]->used_regs[j]) break;
    for (j = 0; j <= MAX_REGS; j++) if (f[i]->used_regs[j]) break;
    GEN ("    cuc_adr_i[5:0] == %i%s\n", j, i < nrf - 1 ? "," : "};");
    GEN ("    cuc_adr_i[5:0] == %i%s\n", j, f[i]->tmp < nrf - 1 ? "," : "};");
  }
  }
 
 
  GEN ("assign i_we = {%i{cuc_stb_i && cuc_we_i}} & i_selected;\n", nrf);
  GEN ("assign i_we = {%i{cuc_stb_i && cuc_we_i}} & i_selected;\n", nrf);
  GEN ("assign i_re = {%i{cuc_stb_i && !cuc_we_i}} & i_selected;\n", nrf);
  GEN ("assign i_re = {%i{cuc_stb_i && !cuc_we_i}} & i_selected;\n", nrf);
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.