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[/] [or1k/] [tags/] [nog_patch_34/] [or1ksim/] [peripheral/] [16450.c] - Diff between revs 1145 and 1153

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Rev 1145	Rev 1153
Line 100...	Line 100...
`uarts[chipsel].istat.txbuf_head = (uarts[chipsel].istat.txbuf_head + 1) % uarts[chipsel].fifo_len;`	`uarts[chipsel].istat.txbuf_head = (uarts[chipsel].istat.txbuf_head + 1) % uarts[chipsel].fifo_len;`
`} else`	`} else`
`uarts[chipsel].regs.txbuf[uarts[chipsel].istat.txbuf_head] = value;`	`uarts[chipsel].regs.txbuf[uarts[chipsel].istat.txbuf_head] = value;`

`uarts[chipsel].regs.lsr &= ~(UART_LSR_TXSERE \| UART_LSR_TXBUFE);`	`uarts[chipsel].regs.lsr &= ~(UART_LSR_TXSERE \| UART_LSR_TXBUFE);`
	`if (uarts[chipsel].regs.iir & UART_IIR_THRI)`
`uarts[chipsel].istat.thre_int = 0;`	`uarts[chipsel].istat.thre_int = 0;`
`break;`	`break;`
`case UART_FCR:`	`case UART_FCR:`
`uarts[chipsel].regs.fcr = value & UART_VALID_FCR;`	`uarts[chipsel].regs.fcr = value & UART_VALID_FCR;`
`if (uarts[chipsel].fifo_len == 1 && (value & UART_FCR_FIE)`	`if (uarts[chipsel].fifo_len == 1 && (value & UART_FCR_FIE)`
Line 196...	Line 197...
`case UART_IER:`	`case UART_IER:`
`value = uarts[chipsel].regs.ier & UART_VALID_IER;`	`value = uarts[chipsel].regs.ier & UART_VALID_IER;`
`break;`	`break;`
`case UART_IIR:`	`case UART_IIR:`
`value = (uarts[chipsel].regs.iir & UART_VALID_IIR) \| 0xc0;`	`value = (uarts[chipsel].regs.iir & UART_VALID_IIR) \| 0xc0;`
`if (uarts[chipsel].regs.ier & UART_IER_THRI)`	`if (uarts[chipsel].regs.iir & UART_IIR_THRI)`
`uarts[chipsel].istat.thre_int = 0;`	`uarts[chipsel].istat.thre_int = 0;`
`break;`	`break;`
`case UART_LCR:`	`case UART_LCR:`
`value = uarts[chipsel].regs.lcr & UART_VALID_LCR;`	`value = uarts[chipsel].regs.lcr & UART_VALID_LCR;`
`break;`	`break;`

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[/] [or1k/] [tags/] [nog_patch_34/] [or1ksim/] [peripheral/] [16450.c] - Diff between revs 1145 and 1153