| Line 35... |
Line 35... |
#include "16450.h"
|
#include "16450.h"
|
#include "sim-config.h"
|
#include "sim-config.h"
|
#include "pic.h"
|
#include "pic.h"
|
#include "vapi.h"
|
#include "vapi.h"
|
|
|
|
#define MIN(a,b) ((a) < (b) ? (a) : (b))
|
|
|
static struct dev_16450 uarts[NR_UARTS];
|
static struct dev_16450 uarts[NR_UARTS];
|
static int thre_int;
|
static int thre_int;
|
|
|
/* Number of clock cycles (one clock cycle is one call to the uart_clock())
|
/* Number of clock cycles (one clock cycle is one call to the uart_clock())
|
before a single character is transmitted or received. */
|
before a single character is transmitted or received. */
|
static unsigned long char_clks(int dll, int dlh, int lcr)
|
static unsigned long char_clks(int dll, int dlh, int lcr)
|
{
|
{
|
float bauds_per_char = 0;
|
float bauds_per_char = 1.;
|
unsigned long char_clks = (dlh << 8) + dll;
|
unsigned long char_clks = ((dlh << 8) + dll) * UART_CLOCK_DIVIDER;
|
|
|
if (lcr & UART_LCR_PARITY)
|
if (lcr & UART_LCR_PARITY)
|
bauds_per_char = bauds_per_char + 1.;
|
bauds_per_char = bauds_per_char + 1.;
|
|
|
/* stop bits 1 or two */
|
/* stop bits 1 or two */
|
| Line 103... |
Line 105... |
uarts[chipsel].regs.lsr |= UART_LSR_TXBUFE;
|
uarts[chipsel].regs.lsr |= UART_LSR_TXBUFE;
|
uarts[chipsel].regs.lsr &= ~UART_LSR_TXSERE;
|
uarts[chipsel].regs.lsr &= ~UART_LSR_TXSERE;
|
|
|
uarts[chipsel].istat.thre_int = 0;
|
uarts[chipsel].istat.thre_int = 0;
|
break;
|
break;
|
|
case UART_FCR:
|
|
uarts[chipsel].regs.fcr = value & UART_VALID_FCR;
|
|
if (uarts[chipsel].fifo_len == 1 && (value & UART_FCR_FIE)
|
|
|| uarts[chipsel].fifo_len != 1 && !(value & UART_FCR_FIE))
|
|
value |= UART_FCR_RRXFI | UART_FCR_RTXFI;
|
|
uarts[chipsel].fifo_len = (value & UART_FCR_FIE) ? 16 : 1;
|
|
if (value & UART_FCR_RTXFI) {
|
|
uarts[chipsel].istat.txbuf_head = uarts[chipsel].istat.txbuf_tail = 0;
|
|
uarts[chipsel].istat.txbuf_full = 0;
|
|
}
|
|
if (value & UART_FCR_RRXFI) {
|
|
uarts[chipsel].istat.rxbuf_head = uarts[chipsel].istat.rxbuf_tail = 0;
|
|
uarts[chipsel].istat.rxbuf_full = 0;
|
|
}
|
|
break;
|
case UART_IER:
|
case UART_IER:
|
uarts[chipsel].regs.ier = value & UART_VALID_IER;
|
uarts[chipsel].regs.ier = value & UART_VALID_IER;
|
|
uarts[chipsel].istat.thre_int = 0;
|
break;
|
break;
|
case UART_LCR:
|
case UART_LCR:
|
uarts[chipsel].regs.lcr = value & UART_VALID_LCR;
|
uarts[chipsel].regs.lcr = value & UART_VALID_LCR;
|
|
uarts[chipsel].char_clks = char_clks(uarts[chipsel].regs.dll, uarts[chipsel].regs.dlh, uarts[chipsel].regs.lcr);
|
break;
|
break;
|
case UART_MCR:
|
case UART_MCR:
|
uarts[chipsel].regs.mcr = value & UART_VALID_MCR;
|
uarts[chipsel].regs.mcr = value & UART_VALID_MCR;
|
break;
|
break;
|
case UART_SCR:
|
case UART_SCR:
|
| Line 150... |
Line 169... |
}
|
}
|
}
|
}
|
|
|
switch (addr % UART_ADDR_SPACE) {
|
switch (addr % UART_ADDR_SPACE) {
|
case UART_RXBUF:
|
case UART_RXBUF:
|
|
{ /* Print out FIFO for debugging */
|
|
int i;
|
|
debug(4, "(%i/%i,%i,%i:", uarts[chipsel].istat.rxbuf_full, uarts[chipsel].fifo_len,
|
|
uarts[chipsel].istat.rxbuf_head, uarts[chipsel].istat.rxbuf_tail);
|
|
for (i = 0; i < uarts[chipsel].istat.rxbuf_full; i++)
|
|
debug(4, "%02x ", uarts[chipsel].regs.rxbuf[(uarts[chipsel].istat.rxbuf_tail + i) % uarts[chipsel].fifo_len]);
|
|
debug(4, ")");
|
|
}
|
if (uarts[chipsel].istat.rxbuf_full) {
|
if (uarts[chipsel].istat.rxbuf_full) {
|
value = uarts[chipsel].regs.rxbuf[uarts[chipsel].istat.rxbuf_tail];
|
value = uarts[chipsel].regs.rxbuf[uarts[chipsel].istat.rxbuf_tail];
|
uarts[chipsel].istat.rxbuf_tail = (uarts[chipsel].istat.rxbuf_tail + 1) % uarts[chipsel].fifo_len;
|
uarts[chipsel].istat.rxbuf_tail = (uarts[chipsel].istat.rxbuf_tail + 1) % uarts[chipsel].fifo_len;
|
uarts[chipsel].istat.rxbuf_full--;
|
uarts[chipsel].istat.rxbuf_full--;
|
}
|
}
|
|
|
if (uarts[chipsel].istat.rxbuf_full)
|
if (uarts[chipsel].istat.rxbuf_full)
|
uarts[chipsel].regs.lsr |= UART_LSR_RDRDY;
|
uarts[chipsel].regs.lsr |= UART_LSR_RDRDY;
|
else
|
else
|
uarts[chipsel].regs.lsr &= ~UART_LSR_RDRDY;
|
uarts[chipsel].regs.lsr &= ~UART_LSR_RDRDY;
|
|
|
|
uarts[chipsel].istat.timeout_count = 0;
|
break;
|
break;
|
case UART_IER:
|
case UART_IER:
|
value = uarts[chipsel].regs.ier & UART_VALID_IER;
|
value = uarts[chipsel].regs.ier & UART_VALID_IER;
|
break;
|
break;
|
case UART_IIR:
|
case UART_IIR:
|
| Line 177... |
Line 206... |
value = 0;
|
value = 0;
|
break;
|
break;
|
case UART_LSR:
|
case UART_LSR:
|
value = uarts[chipsel].regs.lsr & UART_VALID_LSR;
|
value = uarts[chipsel].regs.lsr & UART_VALID_LSR;
|
uarts[chipsel].regs.lsr &=
|
uarts[chipsel].regs.lsr &=
|
~(UART_LSR_OVRRUN | UART_LSR_PARITY
|
~(UART_LSR_OVRRUN | UART_LSR_BREAK | UART_LSR_PARITY
|
| UART_LSR_FRAME | UART_LSR_BREAK);
|
| UART_LSR_FRAME | UART_LSR_RXERR);
|
break;
|
break;
|
case UART_MSR:
|
case UART_MSR:
|
value = uarts[chipsel].regs.msr & UART_VALID_MSR;
|
value = uarts[chipsel].regs.msr & UART_VALID_MSR;
|
uarts[chipsel].regs.msr = 0;
|
uarts[chipsel].regs.msr = 0;
|
break;
|
break;
|
| Line 201... |
Line 230... |
{
|
{
|
int uart;
|
int uart;
|
debug(4, "UART: id %08x, data %08x\n", id, data);
|
debug(4, "UART: id %08x, data %08x\n", id, data);
|
uart = id & VAPI_DEVICE_ID;
|
uart = id & VAPI_DEVICE_ID;
|
uarts[uart].vapi_buf[uarts[uart].vapi_buf_head_ptr] = data;
|
uarts[uart].vapi_buf[uarts[uart].vapi_buf_head_ptr] = data;
|
uarts[uart].vapi_buf_head_ptr = (uarts[uart].vapi_buf_head_ptr + 1) % UART_RX_BUF;
|
uarts[uart].vapi_buf_head_ptr = (uarts[uart].vapi_buf_head_ptr + 1) % UART_VAPI_BUF_LEN;
|
if (uarts[uart].vapi_buf_tail_ptr == uarts[uart].vapi_buf_head_ptr) {
|
if (uarts[uart].vapi_buf_tail_ptr == uarts[uart].vapi_buf_head_ptr) {
|
fprintf (stderr, "FATAL: uart VAPI buffer to small.\n");
|
fprintf (stderr, "FATAL: uart VAPI buffer to small.\n");
|
exit (1);
|
exit (1);
|
}
|
}
|
}
|
}
|
|
|
|
static void send_char (int uart, int bits_send)
|
|
{
|
|
printf ("'%c'\n", uarts[uart].iregs.txser);
|
|
debug(4, "TX \'%c\' via UART%d...\n", uarts[uart].iregs.txser, uart);
|
|
if (uarts[uart].regs.mcr & UART_MCR_LOOP)
|
|
uarts[uart].iregs.loopback = uarts[uart].iregs.txser;
|
|
else {
|
|
/* Send to either VAPI or to file */
|
|
if (config.uarts[uart].vapi_id) {
|
|
int par, pe, fe, nbits;
|
|
int j, data;
|
|
unsigned long packet = 0;
|
|
|
|
nbits = MIN (bits_send, (uarts[uart].regs.lcr & UART_LCR_WLEN8) + 5);
|
|
/* Encode a packet */
|
|
packet = uarts[uart].iregs.txser & ((1 << nbits) - 1);
|
|
|
|
/* Calculate parity */
|
|
for (j = 0, par = 0; j < nbits; j++)
|
|
par ^= (packet >> j) & 1;
|
|
|
|
if (uarts[uart].regs.lcr & UART_LCR_PARITY) {
|
|
if (uarts[uart].regs.lcr & UART_LCR_SPAR) {
|
|
packet |= 1 << nbits;
|
|
} else {
|
|
if (uarts[uart].regs.lcr & UART_LCR_EPAR)
|
|
packet |= par << nbits;
|
|
else
|
|
packet |= (par ^ 1) << nbits;
|
|
}
|
|
nbits++;
|
|
}
|
|
packet |= 1 << (nbits++);
|
|
if (uarts[uart].regs.lcr & UART_LCR_STOP)
|
|
packet |= 1 << (nbits++);
|
|
|
|
/* Decode a packet */
|
|
nbits = (uarts[uart].vapi.lcr & UART_LCR_WLEN8) + 5;
|
|
data = packet & ((1 << nbits) - 1);
|
|
|
|
/* Calculate parity, including parity bit */
|
|
for (j = 0, par = 0; j < nbits + 1; j++)
|
|
par ^= (packet >> j) & 1;
|
|
|
|
if (uarts[uart].vapi.lcr & UART_LCR_PARITY) {
|
|
if (uarts[uart].vapi.lcr & UART_LCR_SPAR) {
|
|
pe = !((packet >> nbits) & 1);
|
|
} else {
|
|
if (uarts[uart].vapi.lcr & UART_LCR_EPAR)
|
|
pe = par != 0;
|
|
else
|
|
pe = par != 1;
|
|
}
|
|
nbits++;
|
|
} else
|
|
pe = 0;
|
|
|
|
fe = ((packet >> (nbits++)) & 1) ^ 1;
|
|
if (uarts[uart].vapi.lcr & UART_LCR_STOP)
|
|
fe |= ((packet >> (nbits++)) & 1) ^ 1;
|
|
|
|
debug (4, "lcr vapi %02x, uart %02x\n", uarts[uart].vapi.lcr, uarts[uart].regs.lcr);
|
|
data |= (uarts[uart].vapi.lcr << 8) | (pe << 16) | (fe << 17) | (uarts[uart].vapi.lcr << 8);
|
|
printf ("vapi_send (%08x, %08x)\n", config.uarts[uart].vapi_id, data);
|
|
debug (4, "vapi_send (%08x, %08x)\n", config.uarts[uart].vapi_id, data);
|
|
vapi_send (config.uarts[uart].vapi_id, data);
|
|
} else {
|
|
fputc((int)(uarts[uart].iregs.txser & 0xFF), uarts[uart].txfs);
|
|
fflush(uarts[uart].txfs);
|
|
}
|
|
}
|
|
uarts[uart].istat.txser_full = 0;
|
|
uarts[uart].istat.txser_clks = 0;
|
|
}
|
|
|
/* Reset. It initializes all registers of all UART devices to zero values,
|
/* Reset. It initializes all registers of all UART devices to zero values,
|
(re)opens all RX/TX file streams and places devices in memory address
|
(re)opens all RX/TX file streams and places devices in memory address
|
space. */
|
space. */
|
void uart_reset()
|
void uart_reset()
|
{
|
{
|
| Line 256... |
Line 360... |
uarts[i].fifo_len = 1;
|
uarts[i].fifo_len = 1;
|
|
|
uarts[i].istat.rxbuf_head = uarts[i].istat.rxbuf_tail = 0;
|
uarts[i].istat.rxbuf_head = uarts[i].istat.rxbuf_tail = 0;
|
uarts[i].istat.txbuf_head = uarts[i].istat.txbuf_tail = 0;
|
uarts[i].istat.txbuf_head = uarts[i].istat.txbuf_tail = 0;
|
|
|
|
uarts[i].istat.break_set = 0;
|
|
uarts[i].istat.timeout_count = 0;
|
|
|
uarts[i].regs.lcr = UART_LCR_RESET;
|
uarts[i].regs.lcr = UART_LCR_RESET;
|
uarts[i].vapi.cur_break = uarts[i].vapi.cur_break_cnt = uarts[i].vapi.next_break = 0;
|
uarts[i].vapi.cur_break = uarts[i].vapi.cur_break_cnt = uarts[i].vapi.next_break = 0;
|
uarts[i].vapi.next_break_cnt = -1;
|
uarts[i].vapi.next_break_cnt = -1;
|
}
|
}
|
}
|
}
|
| Line 276... |
Line 383... |
|
|
/* if txfs is corrupted, skip this uart. */
|
/* if txfs is corrupted, skip this uart. */
|
if (!config.uarts[i].vapi_id && !uarts[i].txfs) continue;
|
if (!config.uarts[i].vapi_id && !uarts[i].txfs) continue;
|
|
|
if (uarts[i].vapi.next_break_cnt >= 0)
|
if (uarts[i].vapi.next_break_cnt >= 0)
|
if (--uarts[i].vapi.next_break_cnt < 0)
|
if (--uarts[i].vapi.next_break_cnt < 0) {
|
uarts[i].vapi.cur_break = uarts[i].vapi.next_break;
|
if (!(uarts[i].vapi.cur_break = uarts[i].vapi.next_break))
|
|
uarts[i].regs.lsr &= ~UART_LSR_BREAK;
|
|
uarts[i].istat.break_set = 0;
|
|
}
|
|
|
/***************** Transmit *****************/
|
/***************** Transmit *****************/
|
if (!uarts[i].istat.txser_full) {
|
if (!uarts[i].istat.txser_full) {
|
uarts[i].regs.lsr |= UART_LSR_TXBUFE;
|
uarts[i].regs.lsr |= UART_LSR_TXBUFE;
|
if (uarts[i].istat.txbuf_full) {
|
if (uarts[i].istat.txbuf_full) {
|
| Line 291... |
Line 401... |
uarts[i].istat.txbuf_full--;
|
uarts[i].istat.txbuf_full--;
|
uarts[i].regs.lsr &= ~UART_LSR_TXSERE;
|
uarts[i].regs.lsr &= ~UART_LSR_TXSERE;
|
uarts[i].istat.thre_int = 1;
|
uarts[i].istat.thre_int = 1;
|
} else
|
} else
|
uarts[i].regs.lsr |= UART_LSR_TXSERE;
|
uarts[i].regs.lsr |= UART_LSR_TXSERE;
|
} else if (uarts[i].char_clks >= uarts[i].istat.txser_clks++) {
|
} else if (uarts[i].char_clks <= uarts[i].istat.txser_clks++) {
|
debug(4, "TX \'%c\' via UART%d...\n", uarts[i].iregs.txser, i);
|
send_char(i, (uarts[i].regs.lcr & UART_LCR_WLEN8) + 5); /* We've sent all bits */
|
if (uarts[i].regs.mcr & UART_MCR_LOOP)
|
|
uarts[i].iregs.loopback = uarts[i].iregs.txser;
|
|
else {
|
|
/* Send to either VAPI or to file */
|
|
if (config.uarts[i].vapi_id) {
|
|
int par, pe, fe, nbits = (uarts[i].regs.lcr & UART_LCR_WLEN8) + 5;
|
|
int j, data;
|
|
unsigned long packet = 0;
|
|
|
|
/* Encode a packet */
|
|
packet = uarts[i].iregs.txser & ((1 << nbits) - 1);
|
|
|
|
/* Calculate parity */
|
|
for (j = 0, par = 0; j < nbits; j++)
|
|
par ^= (packet >> j) & 1;
|
|
|
|
if (uarts[i].regs.lcr & UART_LCR_PARITY) {
|
|
if (uarts[i].regs.lcr & UART_LCR_SPAR) {
|
|
packet |= 1 << nbits;
|
|
} else {
|
} else {
|
if (uarts[i].regs.lcr & UART_LCR_EPAR)
|
/* We are still sending char here*/
|
packet |= par << nbits;
|
|
else
|
|
packet |= (par ^ 1) << nbits;
|
|
}
|
|
nbits++;
|
|
}
|
|
packet |= 1 << (nbits++);
|
|
if (uarts[i].regs.lcr & UART_LCR_STOP)
|
|
packet |= 1 << (nbits++);
|
|
|
|
/* Decode a packet */
|
/* Check if we set the break bit */
|
nbits = (uarts[i].vapi.lcr & UART_LCR_WLEN8) + 5;
|
if (uarts[i].regs.lcr & UART_LCR_SBC) {
|
data = packet & ((1 << nbits) - 1);
|
if (!uarts[i].vapi.break_sent) {
|
|
#if 0
|
/* Calculate parity, including parity bit */
|
/* Send broken frame */
|
for (j = 0, par = 0; j < nbits + 1; j++)
|
int nbits_sent = ((uarts[i].regs.lcr & UART_LCR_WLEN8) + 5) * (uarts[i].istat.txser_clks - 1) / uarts[i].char_clks;
|
par ^= (packet >> j) & 1;
|
send_char(i, nbits_sent);
|
|
#endif
|
if (uarts[i].vapi.lcr & UART_LCR_PARITY) {
|
/* Send one break signal */
|
if (uarts[i].vapi.lcr & UART_LCR_SPAR) {
|
vapi_send (config.uarts[i].vapi_id, UART_LCR_SBC << 8);
|
pe = !((packet >> nbits) & 1);
|
uarts[i].vapi.break_sent = 1;
|
} else {
|
|
if (uarts[i].vapi.lcr & UART_LCR_EPAR)
|
|
pe = par != 0;
|
|
else
|
|
pe = par != 1;
|
|
}
|
|
nbits++;
|
|
} else
|
|
pe = 0;
|
|
|
|
fe = ((packet >> (nbits++)) & 1) ^ 1;
|
|
if (uarts[i].vapi.lcr & UART_LCR_STOP)
|
|
fe |= ((packet >> (nbits++)) & 1) ^ 1;
|
|
|
|
debug (4, "vapi_send (%08x, %08x)\n", config.uarts[i].vapi_id, data | (uarts[i].vapi.lcr << 8) | (pe << 16) | (fe << 17));
|
|
vapi_send (config.uarts[i].vapi_id, data | (uarts[i].vapi.lcr << 8) | (pe << 16) | (fe << 17));
|
|
} else {
|
|
fputc((int)(uarts[i].iregs.txser & 0xFF), uarts[i].txfs);
|
|
fflush(uarts[i].txfs);
|
|
}
|
|
}
|
}
|
|
/* mark as character was sent */
|
uarts[i].istat.txser_full = 0;
|
uarts[i].istat.txser_full = 0;
|
uarts[i].istat.txser_clks = 0;
|
uarts[i].istat.txser_clks = 0;
|
|
} else
|
|
uarts[i].vapi.break_sent = 0;
|
}
|
}
|
|
|
/***************** Receive *****************/
|
/***************** Receive *****************/
|
|
|
/* Is there a break? */
|
/* Is there a break? */
|
if (uarts[i].vapi.cur_break)
|
if (uarts[i].vapi.cur_break) {
|
uarts[i].vapi.cur_break_cnt++;
|
uarts[i].vapi.cur_break_cnt++;
|
if (uarts[i].vapi.cur_break_cnt > MAX_BREAK_COUNT * uarts[i].istat.rxser_clks) {
|
if (uarts[i].vapi.cur_break_cnt > UART_BREAK_COUNT * uarts[i].vapi.char_clks) {
|
if (uarts[i].vapi.cur_break)
|
if (!uarts[i].istat.break_set) {
|
uarts[i].regs.lsr |= UART_LSR_BREAK;
|
uarts[i].istat.break_set = 1;
|
else
|
uarts[i].regs.lsr |= UART_LSR_BREAK | UART_LSR_FRAME | UART_LSR_RXERR | UART_LSR_RDRDY;
|
|
if (uarts[i].regs.lcr & UART_LCR_PARITY) uarts[i].regs.lsr |= UART_LSR_PARITY;
|
|
printf ("[%x]\n", uarts[i].regs.lsr);
|
|
uarts[i].istat.rxser_full = 0;
|
|
uarts[i].istat.rxser_clks = 0;
|
|
|
|
if (uarts[i].istat.rxbuf_full + 1 > uarts[i].fifo_len)
|
|
uarts[i].regs.lsr |= UART_LSR_OVRRUN | UART_LSR_RXERR;
|
|
else {
|
|
uarts[i].regs.rxbuf[uarts[i].istat.rxbuf_head] = 0;
|
|
debug(4, "add %02x\n", 0);
|
|
uarts[i].istat.rxbuf_head = (uarts[i].istat.rxbuf_head + 1) % uarts[i].fifo_len;
|
|
uarts[i].istat.rxbuf_full++;
|
|
}
|
|
uarts[i].regs.lsr |= UART_LSR_RDRDY;
|
|
uarts[i].istat.timeout_count = 0;
|
|
} else
|
uarts[i].vapi.cur_break_cnt = 0;
|
uarts[i].vapi.cur_break_cnt = 0;
|
|
}
|
|
if (uarts[i].istat.rxser_full) {
|
|
uarts[i].istat.rxser_full = 0;
|
|
uarts[i].istat.rxser_clks = 0;
|
|
}
|
} else {
|
} else {
|
if (uarts[i].istat.rxser_full) {
|
if (uarts[i].istat.rxser_full) {
|
if (uarts[i].char_clks >= uarts[i].istat.rxser_clks++) {
|
if (uarts[i].char_clks <= uarts[i].istat.rxser_clks++) {
|
debug(4, "Receiving via UART%d...\n", i);
|
uarts[i].iregs.rxser &= ((1 << ((uarts[i].regs.lcr & 3) + 5)) - 1);
|
|
debug(4, "Receiving 0x%02x'%c' via UART%d...\n", uarts[i].iregs.rxser, uarts[i].iregs.rxser, i);
|
uarts[i].istat.rxser_full = 0;
|
uarts[i].istat.rxser_full = 0;
|
uarts[i].istat.rxser_clks = 0;
|
uarts[i].istat.rxser_clks = 0;
|
|
|
if (++uarts[i].istat.rxbuf_full > uarts[i].fifo_len)
|
if (uarts[i].istat.rxbuf_full + 1 > uarts[i].fifo_len)
|
uarts[i].regs.lsr |= UART_LSR_OVRRUN;
|
uarts[i].regs.lsr |= UART_LSR_OVRRUN | UART_LSR_RXERR;
|
else {
|
else {
|
uarts[i].regs.rxbuf[uarts[i].istat.rxbuf_head] = uarts[i].iregs.rxser & 0xFF;
|
debug(4, "add %02x\n", uarts[i].iregs.rxser);
|
|
uarts[i].regs.rxbuf[uarts[i].istat.rxbuf_head] = uarts[i].iregs.rxser;
|
uarts[i].istat.rxbuf_head = (uarts[i].istat.rxbuf_head + 1) % uarts[i].fifo_len;
|
uarts[i].istat.rxbuf_head = (uarts[i].istat.rxbuf_head + 1) % uarts[i].fifo_len;
|
uarts[i].istat.rxbuf_full++;
|
uarts[i].istat.rxbuf_full++;
|
}
|
}
|
uarts[i].regs.lsr |= UART_LSR_RDRDY;
|
uarts[i].regs.lsr |= UART_LSR_RDRDY;
|
|
uarts[i].istat.timeout_count = 0;
|
}
|
}
|
}
|
}
|
}
|
}
|
|
|
/* Check if there is something waiting, and put it into rxser */
|
/* Check if there is something waiting, and put it into rxser */
|
| Line 406... |
Line 495... |
if (uarts[i].istat.rxser_full)
|
if (uarts[i].istat.rxser_full)
|
break;
|
break;
|
while (!received) {
|
while (!received) {
|
if (uarts[i].vapi_buf_head_ptr != uarts[i].vapi_buf_tail_ptr) {
|
if (uarts[i].vapi_buf_head_ptr != uarts[i].vapi_buf_tail_ptr) {
|
unsigned long data = uarts[i].vapi_buf[uarts[i].vapi_buf_tail_ptr];
|
unsigned long data = uarts[i].vapi_buf[uarts[i].vapi_buf_tail_ptr];
|
uarts[i].vapi_buf_tail_ptr = (uarts[i].vapi_buf_tail_ptr + 1) % uarts[i].fifo_len;
|
debug(4, "Handling: %08x (%i,%i)\n", data, uarts[i].vapi_buf_head_ptr, uarts[i].vapi_buf_tail_ptr);
|
|
uarts[i].vapi_buf_tail_ptr = (uarts[i].vapi_buf_tail_ptr + 1) % UART_VAPI_BUF_LEN;
|
switch (data >> 24) {
|
switch (data >> 24) {
|
case 0x00:
|
case 0x00:
|
uarts[i].vapi.lcr = (data >> 8) & 0xff;
|
uarts[i].vapi.lcr = (data >> 8) & 0xff;
|
/* Put data into rx fifo */
|
/* Put data into rx fifo */
|
uarts[i].vapi.char_clks = char_clks (uarts[i].vapi.dll, uarts[i].vapi.dlh, uarts[i].vapi.lcr);
|
uarts[i].vapi.char_clks = char_clks (uarts[i].vapi.dll, uarts[i].vapi.dlh, uarts[i].vapi.lcr);
|
if (uarts[i].vapi.lcr != uarts[i].regs.lcr || uarts[i].vapi.char_clks != uarts[i].char_clks
|
if ((uarts[i].vapi.lcr & ~UART_LCR_SBC) != (uarts[i].regs.lcr & ~UART_LCR_SBC)
|
|
|| uarts[i].vapi.char_clks != uarts[i].char_clks
|
|| uarts[i].vapi.skew < -MAX_SKEW || uarts[i].vapi.skew > MAX_SKEW) {
|
|| uarts[i].vapi.skew < -MAX_SKEW || uarts[i].vapi.skew > MAX_SKEW) {
|
debug (3, "WARNING: unmatched VAPI and uart modes.\n");
|
debug (3, "WARNING: unmatched VAPI (%02x) and uart (%02x) modes.\n",
|
|
uarts[i].vapi.lcr & ~UART_LCR_SBC, uarts[i].regs.lcr & ~UART_LCR_SBC);
|
/* Set error bits */
|
/* Set error bits */
|
uarts[i].regs.lsr |= UART_LSR_PARITY | UART_LSR_FRAME;
|
uarts[i].regs.lsr |= UART_LSR_FRAME | UART_LSR_RXERR;
|
break;
|
if (uarts[i].regs.lcr & UART_LCR_PARITY) uarts[i].regs.lsr |= UART_LSR_PARITY;
|
} else {
|
}
|
uarts[i].iregs.rxser = data & 0xff;
|
uarts[i].iregs.rxser = data & 0xff;
|
uarts[i].istat.rxser_full = 1;
|
uarts[i].istat.rxser_full = 1;
|
}
|
|
received = 1;
|
received = 1;
|
break;
|
break;
|
case 0x01:
|
case 0x01:
|
uarts[i].vapi.dll = (data >> 0) & 0xff;
|
uarts[i].vapi.dll = (data >> 0) & 0xff;
|
uarts[i].vapi.dlh = (data >> 8) & 0xff;
|
uarts[i].vapi.dlh = (data >> 8) & 0xff;
|
| Line 470... |
Line 561... |
uarts[i].regs.msr |= ((uarts[i].regs.mcr & UART_MCR_AUX1) << 4);
|
uarts[i].regs.msr |= ((uarts[i].regs.mcr & UART_MCR_AUX1) << 4);
|
uarts[i].regs.msr |= ((uarts[i].regs.mcr & UART_MCR_RTS) << 3);
|
uarts[i].regs.msr |= ((uarts[i].regs.mcr & UART_MCR_RTS) << 3);
|
uarts[i].regs.msr |= ((uarts[i].regs.mcr & UART_MCR_DTR) << 5);
|
uarts[i].regs.msr |= ((uarts[i].regs.mcr & UART_MCR_DTR) << 5);
|
}
|
}
|
|
|
|
if (uarts[i].regs.lsr & UART_LSR_RDRDY)
|
|
uarts[i].istat.timeout_count++;
|
|
|
/* Interrupt detection in proper priority order. */
|
/* Interrupt detection in proper priority order. */
|
uarts[i].regs.iir = UART_IIR_NO_INT;
|
uarts[i].regs.iir = UART_IIR_NO_INT;
|
if (uarts[i].regs.ier & UART_IER_RLSI &&
|
if (uarts[i].regs.ier & UART_IER_RLSI && /* Receiver LS */
|
uarts[i].regs.lsr & (UART_LSR_OVRRUN | UART_LSR_PARITY
|
uarts[i].regs.lsr & (UART_LSR_OVRRUN | UART_LSR_PARITY
|
| UART_LSR_FRAME | UART_LSR_BREAK)) {
|
| UART_LSR_FRAME | UART_LSR_BREAK)) {
|
uarts[i].regs.iir = UART_IIR_RLSI;
|
uarts[i].regs.iir = UART_IIR_RLSI;
|
}
|
} else if ((uarts[i].regs.ier & UART_IER_RDI) /* RD available */
|
else if (uarts[i].regs.ier & UART_IER_RDI &&
|
&& (uarts[i].istat.rxbuf_full >= UART_FIFO_TRIGGER(uarts[i].regs.fcr >> 6))
|
uarts[i].regs.lsr & UART_LSR_RDRDY) {
|
&& (uarts[i].regs.lsr & UART_LSR_RDRDY)) {
|
uarts[i].regs.iir = UART_IIR_RDI;
|
uarts[i].regs.iir = UART_IIR_RDI;
|
}
|
} else if ((uarts[i].regs.ier & UART_IER_RDI) /* timeout */
|
else if (uarts[i].regs.ier & UART_IER_THRI &&
|
&& (uarts[i].istat.timeout_count >= UART_CHAR_TIMEOUT * uarts[i].char_clks)) {
|
|
uarts[i].regs.iir = UART_IIR_CTI;
|
|
} else if (uarts[i].regs.ier & UART_IER_THRI && /* Transm. empty */
|
uarts[i].regs.lsr & UART_LSR_TXBUFE &&
|
uarts[i].regs.lsr & UART_LSR_TXBUFE &&
|
uarts[i].istat.thre_int == 1) {
|
uarts[i].istat.thre_int == 1) {
|
uarts[i].regs.iir = UART_IIR_THRI;
|
uarts[i].regs.iir = UART_IIR_THRI;
|
}
|
} else if (uarts[i].regs.ier & UART_IER_MSI && /* Modem status */
|
else if (uarts[i].regs.ier & UART_IER_MSI &&
|
|
uarts[i].regs.msr & (UART_MSR_DCTS | UART_MSR_DDSR
|
uarts[i].regs.msr & (UART_MSR_DCTS | UART_MSR_DDSR
|
| UART_MSR_TERI | UART_MSR_DDCD)) {
|
| UART_MSR_TERI | UART_MSR_DDCD)) {
|
uarts[i].regs.iir = UART_IIR_MSI;
|
uarts[i].regs.iir = UART_IIR_MSI;
|
}
|
}
|
if (!(uarts[i].regs.iir & UART_IIR_NO_INT))
|
if (!(uarts[i].regs.iir & UART_IIR_NO_INT)) {
|
|
debug (4, "uarts[i].regs.iir = %i\t", uarts[i].regs.iir);
|
report_interrupt(config.uarts[i].irq);
|
report_interrupt(config.uarts[i].irq);
|
}
|
}
|
}
|
}
|
|
}
|
|
|
/* Print register values on stdout. */
|
/* Print register values on stdout. */
|
void uart_status()
|
void uart_status()
|
{
|
{
|
int i, j;
|
int i, j;
|
