| Line 1... |
Line 1... |
/* dma.c -- Simulation of DMA
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/* dma.c -- Simulation of DMA
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Copyright (C) 2001 by Erez Volk, erez@mailandnews.com
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Copyright (C) 2001 by Erez Volk, erez@opencores.org
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This file is part of OpenRISC 1000 Architectural Simulator.
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This file is part of OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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| Line 26... |
Line 26... |
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#include "dma.h"
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#include "dma.h"
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#include "sim-config.h"
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#include "sim-config.h"
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#include "trace.h"
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#include "trace.h"
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#include "pic.h"
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#include "pic.h"
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#include "abstract.h"
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#include "fields.h"
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#include "fields.h"
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/* TODO List:
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* - "Restarting DMA Transfers"
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*/
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/* The representation of the DMA controllers */
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/* The representation of the DMA controllers */
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static struct dma_controller dmas[NR_DMAS];
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static struct dma_controller dmas[NR_DMAS];
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static unsigned long dma_read32( unsigned long addr );
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static void dma_write32( unsigned long addr, unsigned long value );
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static unsigned long dma_read_ch_csr( struct dma_channel *channel );
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static unsigned long dma_read_ch_csr( struct dma_channel *channel );
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static void dma_write_ch_csr( struct dma_channel *channel, unsigned long value );
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static void dma_write_ch_csr( struct dma_channel *channel, unsigned long value );
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static void dma_controller_clock( struct dma_controller *dma );
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static void dma_controller_clock( struct dma_controller *dma );
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static void dma_load_descriptor( struct dma_channel *channel );
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static void dma_load_descriptor( struct dma_channel *channel );
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static void dma_init_transfer( struct dma_channel *channel );
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static void dma_init_transfer( struct dma_channel *channel );
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| Line 54... |
Line 54... |
{
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{
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unsigned i;
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unsigned i;
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memset( dmas, 0, sizeof(dmas) );
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memset( dmas, 0, sizeof(dmas) );
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for ( i = 0; i < NR_DMAS; ++ i )
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for ( i = 0; i < NR_DMAS; ++ i ) {
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{
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struct dma_controller *dma = &(dmas[i]);
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struct dma_controller *dma = &(dmas[i]);
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unsigned channel_number;
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unsigned channel_number;
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dma->baseaddr = config.dmas[i].baseaddr;
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dma->baseaddr = config.dmas[i].baseaddr;
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for ( channel_number = 0; channel_number < DMA_NUM_CHANNELS; ++ channel_number )
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dma->irq = config.dmas[i].irq;
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{
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for ( channel_number = 0; channel_number < DMA_NUM_CHANNELS; ++ channel_number ) {
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dma->ch[channel_number].controller = &(dmas[i]);
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dma->ch[channel_number].controller = &(dmas[i]);
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dma->ch[channel_number].channel_number = channel_number;
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dma->ch[channel_number].channel_number = channel_number;
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dma->ch[channel_number].channel_mask = 1LU << channel_number;
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dma->ch[channel_number].channel_mask = 1LU << channel_number;
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dma->ch[channel_number].regs.am0 = dma->ch[channel_number].regs.am1 = 0xFFFFFFFC;
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dma->ch[channel_number].regs.am0 = dma->ch[channel_number].regs.am1 = 0xFFFFFFFC;
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}
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}
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if ( dma->baseaddr != 0 )
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if ( dma->baseaddr != 0 )
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register_memoryarea( dma->baseaddr, DMA_ADDR_SPACE, dma_read, dma_write );
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register_memoryarea( dma->baseaddr, DMA_ADDR_SPACE, 4, dma_read32, dma_write32, 0 );
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}
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}
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}
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}
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/* Print register values on stdout */
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/* Print register values on stdout */
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void dma_status( void )
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void dma_status( void )
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{
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{
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unsigned i, j;
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unsigned i, j;
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for ( i = 0; i < NR_DMAS; ++ i )
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for ( i = 0; i < NR_DMAS; ++ i ) {
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{
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struct dma_controller *dma = &(dmas[i]);
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struct dma_controller *dma = &(dmas[i]);
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if ( dma->baseaddr == 0 )
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if ( dma->baseaddr == 0 )
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continue;
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continue;
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| Line 91... |
Line 89... |
printf( "INT_MSK_A : 0x%08lX\n", dma->regs.int_msk_a );
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printf( "INT_MSK_A : 0x%08lX\n", dma->regs.int_msk_a );
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printf( "INT_MSK_B : 0x%08lX\n", dma->regs.int_msk_b );
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printf( "INT_MSK_B : 0x%08lX\n", dma->regs.int_msk_b );
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printf( "INT_SRC_A : 0x%08lX\n", dma->regs.int_src_a );
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printf( "INT_SRC_A : 0x%08lX\n", dma->regs.int_src_a );
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printf( "INT_SRC_B : 0x%08lX\n", dma->regs.int_src_b );
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printf( "INT_SRC_B : 0x%08lX\n", dma->regs.int_src_b );
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for ( j = 0; j < DMA_NUM_CHANNELS; ++ j )
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for ( j = 0; j < DMA_NUM_CHANNELS; ++ j ) {
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{
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struct dma_channel *channel = &(dma->ch[j]);
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struct dma_channel *channel = &(dma->ch[j]);
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if ( !channel->referenced )
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if ( !channel->referenced )
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continue;
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continue;
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printf( "CH%u_CSR : 0x%08lX\n", j, channel->regs.csr );
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printf( "CH%u_CSR : 0x%08lX\n", j, channel->regs.csr );
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printf( "CH%u_SZ : 0x%08lX\n", j, channel->regs.sz );
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printf( "CH%u_SZ : 0x%08lX\n", j, channel->regs.sz );
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| Line 110... |
Line 107... |
}
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}
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}
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}
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/* Read a register */
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/* Read a register */
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unsigned long dma_read( unsigned long addr )
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unsigned long dma_read32( unsigned long addr )
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{
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{
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unsigned i;
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unsigned i;
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struct dma_controller *dma = NULL;
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struct dma_controller *dma = NULL;
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for ( i = 0; i < NR_DMAS && dma == NULL; ++ i )
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for ( i = 0; i < NR_DMAS && dma == NULL; ++ i ) {
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{
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if ( addr >= dmas[i].baseaddr && addr < dmas[i].baseaddr + DMA_ADDR_SPACE )
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if ( addr >= dmas[i].baseaddr && addr < dmas[i].baseaddr + DMA_ADDR_SPACE )
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dma = &(dmas[i]);
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dma = &(dmas[i]);
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}
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}
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/* verify we found a controller */
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/* verify we found a controller */
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if ( dma == NULL )
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if ( dma == NULL ) {
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{
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fprintf( stderr, "dma_read32( 0x%08lX ): Out of range\n", addr );
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debug( "dma_read( 0x%08lX ): Out of range\n", addr );
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cont_run = 0;
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cont_run = 0;
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return 0;
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return 0;
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}
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}
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addr -= dma->baseaddr;
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addr -= dma->baseaddr;
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if ( addr % 4 != 0 )
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if ( addr % 4 != 0 ) {
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{
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fprintf( stderr, "dma_read32( 0x%08lX ): Not register-aligned\n", addr + dma->baseaddr );
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debug( "dma_read( 0x%08lX ): Not register-aligned\n", addr + dma->baseaddr );
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cont_run = 0;
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cont_run = 0;
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return 0;
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return 0;
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}
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}
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/* case of global (not per-channel) registers */
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/* case of global (not per-channel) registers */
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if ( addr < DMA_CH_BASE )
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if ( addr < DMA_CH_BASE ) {
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{
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switch( addr ) {
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switch( addr )
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{
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case DMA_CSR: return dma->regs.csr;
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case DMA_CSR: return dma->regs.csr;
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case DMA_INT_MSK_A: return dma->regs.int_msk_a;
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case DMA_INT_MSK_A: return dma->regs.int_msk_a;
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case DMA_INT_MSK_B: return dma->regs.int_msk_b;
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case DMA_INT_MSK_B: return dma->regs.int_msk_b;
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case DMA_INT_SRC_A: {
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case DMA_INT_SRC_A: return dma->regs.int_src_a;
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/* TODO: Doc doesn't say clear the bits, but this looks right. Check it */
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case DMA_INT_SRC_B: return dma->regs.int_src_b;
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unsigned long result = dma->regs.int_src_a;
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dma->regs.int_src_a = 0;
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return result;
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}
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case DMA_INT_SRC_B: {
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unsigned long result = dma->regs.int_src_b;
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dma->regs.int_src_b = 0;
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return result;
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}
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default:
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default:
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debug( "dma_read( 0x%08lX ): Illegal register\n", addr + dma->baseaddr );
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fprintf( stderr, "dma_read32( 0x%08lX ): Illegal register\n", addr + dma->baseaddr );
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cont_run = 0;
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cont_run = 0;
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return 0;
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return 0;
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}
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}
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}
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} else {
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else
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{
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/* case of per-channel registers */
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/* case of per-channel registers */
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unsigned chno = (addr - DMA_CH_BASE) / DMA_CH_SIZE;
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unsigned chno = (addr - DMA_CH_BASE) / DMA_CH_SIZE;
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addr = (addr - DMA_CH_BASE) % DMA_CH_SIZE;
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addr = (addr - DMA_CH_BASE) % DMA_CH_SIZE;
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switch( addr )
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switch( addr ) {
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{
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case DMA_CH_CSR: return dma_read_ch_csr( &(dma->ch[chno]) );
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case DMA_CH_CSR: return dma_read_ch_csr( &(dma->ch[chno]) );
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case DMA_CH_SZ: return dma->ch[chno].regs.sz;
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case DMA_CH_SZ: return dma->ch[chno].regs.sz;
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case DMA_CH_A0: return dma->ch[chno].regs.a0;
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case DMA_CH_A0: return dma->ch[chno].regs.a0;
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case DMA_CH_AM0: return dma->ch[chno].regs.am0;
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case DMA_CH_AM0: return dma->ch[chno].regs.am0;
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case DMA_CH_A1: return dma->ch[chno].regs.a1;
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case DMA_CH_A1: return dma->ch[chno].regs.a1;
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| Line 200... |
Line 180... |
}
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}
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/* Write a register */
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/* Write a register */
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void dma_write( unsigned long addr, unsigned long value )
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void dma_write32( unsigned long addr, unsigned long value )
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{
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{
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unsigned i;
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unsigned i;
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struct dma_controller *dma = NULL;
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struct dma_controller *dma = NULL;
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/* Find which controller this is */
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/* Find which controller this is */
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for ( i = 0; i < NR_DMAS && dma == NULL; ++ i )
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for ( i = 0; i < NR_DMAS && dma == NULL; ++ i ) {
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{
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if ( (addr >= dmas[i].baseaddr) && (addr < dmas[i].baseaddr + DMA_ADDR_SPACE) )
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if ( (addr >= dmas[i].baseaddr) && (addr < dmas[i].baseaddr + DMA_ADDR_SPACE) )
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dma = &(dmas[i]);
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dma = &(dmas[i]);
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}
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}
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/* verify we found a controller */
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/* verify we found a controller */
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if ( dma == NULL )
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if ( dma == NULL ) {
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{
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fprintf( stderr, "dma_write32( 0x%08lX ): Out of range\n", addr );
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debug( "dma_write( 0x%08lX ): Out of range\n", addr );
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cont_run = 0;
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cont_run = 0;
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return;
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return;
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}
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}
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addr -= dma->baseaddr;
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addr -= dma->baseaddr;
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|
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if ( addr % 4 != 0 )
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if ( addr % 4 != 0 ) {
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{
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fprintf( stderr, "dma_write32( 0x%08lX, 0x%08lX ): Not register-aligned\n", addr + dma->baseaddr, value );
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debug( "dma_write( 0x%08lX ): Not register-aligned\n", addr + dma->baseaddr );
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cont_run = 0;
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cont_run = 0;
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return;
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return;
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}
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}
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|
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/* case of global (not per-channel) registers */
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/* case of global (not per-channel) registers */
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if ( addr < DMA_CH_BASE )
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if ( addr < DMA_CH_BASE ) {
|
{
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switch( addr ) {
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switch( addr )
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{
|
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case DMA_CSR:
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case DMA_CSR:
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if ( TEST_FLAG( value, DMA_CSR, PAUSE ) )
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if ( TEST_FLAG( value, DMA_CSR, PAUSE ) )
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debug( "dma: PAUSE not implemented\n" );
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fprintf( stderr, "dma: PAUSE not implemented\n" );
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break;
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break;
|
|
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case DMA_INT_MSK_A: dma->regs.int_msk_a = value; break;
|
case DMA_INT_MSK_A: dma->regs.int_msk_a = value; break;
|
case DMA_INT_MSK_B: dma->regs.int_msk_b = value; break;
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case DMA_INT_MSK_B: dma->regs.int_msk_b = value; break;
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case DMA_INT_SRC_A: dma->regs.int_src_a = value; break;
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case DMA_INT_SRC_A: dma->regs.int_src_a = value; break;
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case DMA_INT_SRC_B: dma->regs.int_src_b = value; break;
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case DMA_INT_SRC_B: dma->regs.int_src_b = value; break;
|
default:
|
default:
|
debug( "dma_write( 0x%08lX ): Illegal register\n", addr + dma->baseaddr );
|
fprintf( stderr, "dma_write32( 0x%08lX ): Illegal register\n", addr + dma->baseaddr );
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cont_run = 0;
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cont_run = 0;
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return;
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return;
|
}
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}
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}
|
} else {
|
else
|
|
{
|
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/* case of per-channel registers */
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/* case of per-channel registers */
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unsigned chno = (addr - DMA_CH_BASE) / DMA_CH_SIZE;
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unsigned chno = (addr - DMA_CH_BASE) / DMA_CH_SIZE;
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struct dma_channel *channel = &(dma->ch[chno]);
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struct dma_channel *channel = &(dma->ch[chno]);
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channel->referenced = 1;
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channel->referenced = 1;
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addr = (addr - DMA_CH_BASE) % DMA_CH_SIZE;
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addr = (addr - DMA_CH_BASE) % DMA_CH_SIZE;
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switch( addr )
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switch( addr ) {
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{
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case DMA_CSR: dma_write_ch_csr( &(dma->ch[chno]), value ); break;
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case DMA_CSR: dma_write_ch_csr( &(dma->ch[chno]), value ); break;
|
case DMA_CH_SZ: channel->regs.sz = value; break;
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case DMA_CH_SZ: channel->regs.sz = value; break;
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case DMA_CH_A0: channel->regs.a0 = value; break;
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case DMA_CH_A0: channel->regs.a0 = value; break;
|
case DMA_CH_AM0: channel->regs.am0 = value; break;
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case DMA_CH_AM0: channel->regs.am0 = value; break;
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case DMA_CH_A1: channel->regs.a1 = value; break;
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case DMA_CH_A1: channel->regs.a1 = value; break;
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| Line 307... |
Line 279... |
void clear_dma_nd_i( unsigned dma_controller, unsigned channel )
|
void clear_dma_nd_i( unsigned dma_controller, unsigned channel )
|
{
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{
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dmas[dma_controller].ch[channel].dma_nd_i = 0;
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dmas[dma_controller].ch[channel].dma_nd_i = 0;
|
}
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}
|
|
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unsigned check_dma_acq_o( unsigned dma_controller, unsigned channel )
|
unsigned check_dma_ack_o( unsigned dma_controller, unsigned channel )
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{
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{
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return dmas[dma_controller].ch[channel].dma_acq_o;
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return dmas[dma_controller].ch[channel].dma_ack_o;
|
}
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}
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|
|
|
|
|
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/* Simulation hook. Must be called every clock cycle to simulate DMA. */
|
/* Simulation hook. Must be called every clock cycle to simulate DMA. */
|
void dma_clock()
|
void dma_clock()
|
{
|
{
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unsigned i;
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unsigned i;
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for ( i = 0; i < NR_DMAS; ++ i )
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for ( i = 0; i < NR_DMAS; ++ i ) {
|
{
|
|
if ( dmas[i].baseaddr != 0 )
|
if ( dmas[i].baseaddr != 0 )
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dma_controller_clock( &(dmas[i]) );
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dma_controller_clock( &(dmas[i]) );
|
}
|
}
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}
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}
|
|
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| Line 335... |
Line 306... |
void dma_controller_clock( struct dma_controller *dma )
|
void dma_controller_clock( struct dma_controller *dma )
|
{
|
{
|
unsigned chno, i;
|
unsigned chno, i;
|
int breakpoint = 0;
|
int breakpoint = 0;
|
|
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for ( chno = 0; chno < DMA_NUM_CHANNELS; ++ chno )
|
for ( chno = 0; chno < DMA_NUM_CHANNELS; ++ chno ) {
|
{
|
|
struct dma_channel *channel = &(dma->ch[chno]);
|
struct dma_channel *channel = &(dma->ch[chno]);
|
|
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/* check if this channel is enabled */
|
/* check if this channel is enabled */
|
if ( !TEST_FLAG( channel->regs.csr, DMA_CH_CSR, CH_EN ) )
|
if ( !TEST_FLAG( channel->regs.csr, DMA_CH_CSR, CH_EN ) )
|
continue;
|
continue;
|
|
|
/* Do we need to abort? */
|
/* Do we need to abort? */
|
if ( TEST_FLAG( channel->regs.csr, DMA_CH_CSR, STOP ) )
|
if ( TEST_FLAG( channel->regs.csr, DMA_CH_CSR, STOP ) ) {
|
{
|
fprintf( stderr, "DMA: STOP requested\n" );
|
debug( "DMA: STOP requested\n" );
|
|
CLEAR_FLAG( channel->regs.csr, DMA_CH_CSR, CH_EN );
|
CLEAR_FLAG( channel->regs.csr, DMA_CH_CSR, CH_EN );
|
CLEAR_FLAG( channel->regs.csr, DMA_CH_CSR, BUSY );
|
CLEAR_FLAG( channel->regs.csr, DMA_CH_CSR, BUSY );
|
SET_FLAG( channel->regs.csr, DMA_CH_CSR, ERR );
|
SET_FLAG( channel->regs.csr, DMA_CH_CSR, ERR );
|
|
|
if ( TEST_FLAG( channel->regs.csr, DMA_CH_CSR, INE_ERR ) &&
|
if ( TEST_FLAG( channel->regs.csr, DMA_CH_CSR, INE_ERR ) &&
|
(channel->controller->regs.int_msk_a & channel->channel_mask) )
|
(channel->controller->regs.int_msk_a & channel->channel_mask) ) {
|
{
|
|
SET_FLAG( channel->regs.csr, DMA_CH_CSR, INT_ERR );
|
SET_FLAG( channel->regs.csr, DMA_CH_CSR, INT_ERR );
|
channel->controller->regs.int_src_a = channel->channel_mask;
|
channel->controller->regs.int_src_a = channel->channel_mask;
|
report_interrupt( INT_DMA );
|
report_interrupt( channel->controller->irq );
|
}
|
}
|
|
|
continue;
|
continue;
|
}
|
}
|
|
|
/* In HW Handshake mode, only work when dma_req_i asserted */
|
/* In HW Handshake mode, only work when dma_req_i asserted */
|
if ( TEST_FLAG( channel->regs.csr, DMA_CH_CSR, MODE ) &&
|
if ( TEST_FLAG( channel->regs.csr, DMA_CH_CSR, MODE ) &&
|
!channel->dma_req_i )
|
!channel->dma_req_i ) {
|
{
|
fprintf( stderr, "DMA: Waiting for HW handshake\n" );
|
debug( "DMA: Waiting for HW handshake\n" );
|
|
continue;
|
continue;
|
}
|
}
|
|
|
/* If this is the first cycle of the transfer, initialize our state */
|
/* If this is the first cycle of the transfer, initialize our state */
|
if ( !TEST_FLAG( channel->regs.csr, DMA_CH_CSR, BUSY ) )
|
if ( !TEST_FLAG( channel->regs.csr, DMA_CH_CSR, BUSY ) ) {
|
{
|
|
CLEAR_FLAG( channel->regs.csr, DMA_CH_CSR, DONE );
|
CLEAR_FLAG( channel->regs.csr, DMA_CH_CSR, DONE );
|
CLEAR_FLAG( channel->regs.csr, DMA_CH_CSR, ERR );
|
CLEAR_FLAG( channel->regs.csr, DMA_CH_CSR, ERR );
|
SET_FLAG( channel->regs.csr, DMA_CH_CSR, BUSY );
|
SET_FLAG( channel->regs.csr, DMA_CH_CSR, BUSY );
|
|
|
/* If using linked lists, copy the appropriate fields to our registers */
|
/* If using linked lists, copy the appropriate fields to our registers */
|
| Line 387... |
Line 353... |
|
|
/* Set our internal status */
|
/* Set our internal status */
|
dma_init_transfer( channel );
|
dma_init_transfer( channel );
|
|
|
/* Might need to skip descriptor */
|
/* Might need to skip descriptor */
|
if ( CHANNEL_ND_I( channel ) )
|
if ( CHANNEL_ND_I( channel ) ) {
|
{
|
fprintf( stderr, "DMA: dma_nd_i asserted before dma_req_i, skipping descriptor\n" );
|
debug( "DMA: dma_nd_i asserted before dma_req_i, skipping descriptor\n" );
|
|
dma_channel_terminate_transfer( channel, 0 );
|
dma_channel_terminate_transfer( channel, 0 );
|
continue;
|
continue;
|
}
|
}
|
}
|
}
|
|
|
| Line 404... |
Line 369... |
masked_increase( &(channel->source), channel->source_mask );
|
masked_increase( &(channel->source), channel->source_mask );
|
masked_increase( &(channel->destination), channel->destination_mask );
|
masked_increase( &(channel->destination), channel->destination_mask );
|
++ channel->words_transferred;
|
++ channel->words_transferred;
|
|
|
/* Have we finished a whole chunk? */
|
/* Have we finished a whole chunk? */
|
channel->dma_acq_o = (channel->words_transferred % channel->chunk_size == 0);
|
channel->dma_ack_o = (channel->words_transferred % channel->chunk_size == 0);
|
|
|
/* When done with a chunk, check for dma_nd_i */
|
/* When done with a chunk, check for dma_nd_i */
|
if ( CHANNEL_ND_I( channel ) )
|
if ( CHANNEL_ND_I( channel ) ) {
|
{
|
fprintf( stderr, "DMA: dma_nd_i asserted, \n" );
|
debug( "DMA: dma_nd_i asserted, \n" );
|
|
dma_channel_terminate_transfer( channel, 0 );
|
dma_channel_terminate_transfer( channel, 0 );
|
continue;
|
continue;
|
}
|
}
|
|
|
/* Are we done? */
|
/* Are we done? */
|
| Line 463... |
Line 427... |
|
|
/* Take care of transfer termination */
|
/* Take care of transfer termination */
|
void dma_channel_terminate_transfer( struct dma_channel *channel, int generate_interrupt )
|
void dma_channel_terminate_transfer( struct dma_channel *channel, int generate_interrupt )
|
{
|
{
|
/* Might be working in a linked list */
|
/* Might be working in a linked list */
|
if ( channel->load_next_descriptor_when_done )
|
if ( channel->load_next_descriptor_when_done ) {
|
{
|
|
dma_load_descriptor( channel );
|
dma_load_descriptor( channel );
|
dma_init_transfer( channel );
|
dma_init_transfer( channel );
|
return;
|
return;
|
}
|
}
|
|
|
/* Might be in auto-restart mode */
|
/* Might be in auto-restart mode */
|
if ( TEST_FLAG( channel->regs.csr, DMA_CH_CSR, ARS ) )
|
if ( TEST_FLAG( channel->regs.csr, DMA_CH_CSR, ARS ) ) {
|
{
|
|
dma_init_transfer( channel );
|
dma_init_transfer( channel );
|
return;
|
return;
|
}
|
}
|
|
|
/* If needed, write amount of data transferred back to memory */
|
/* If needed, write amount of data transferred back to memory */
|
if ( TEST_FLAG( channel->regs.csr, DMA_CH_CSR, SZ_WB ) &&
|
if ( TEST_FLAG( channel->regs.csr, DMA_CH_CSR, SZ_WB ) &&
|
TEST_FLAG( channel->regs.csr, DMA_CH_CSR, USE_ED ) )
|
TEST_FLAG( channel->regs.csr, DMA_CH_CSR, USE_ED ) ) {
|
{
|
|
int breakpoint = 0;
|
int breakpoint = 0;
|
unsigned long desc_csr = eval_mem32( channel->regs.desc + DMA_DESC_CSR, &breakpoint );
|
unsigned long desc_csr = eval_mem32( channel->regs.desc + DMA_DESC_CSR, &breakpoint );
|
/* TODO: What should we write back? Doc says "total number of remaining bytes" !? */
|
/* TODO: What should we write back? Doc says "total number of remaining bytes" !? */
|
unsigned long remaining_words = channel->total_size - channel->words_transferred;
|
unsigned long remaining_words = channel->total_size - channel->words_transferred;
|
SET_FIELD( channel->regs.sz, DMA_DESC_CSR, TOT_SZ, remaining_words );
|
SET_FIELD( channel->regs.sz, DMA_DESC_CSR, TOT_SZ, remaining_words );
|
| Line 495... |
Line 456... |
SET_FLAG( channel->regs.csr, DMA_CH_CSR, DONE );
|
SET_FLAG( channel->regs.csr, DMA_CH_CSR, DONE );
|
CLEAR_FLAG( channel->regs.csr, DMA_CH_CSR, ERR );
|
CLEAR_FLAG( channel->regs.csr, DMA_CH_CSR, ERR );
|
CLEAR_FLAG( channel->regs.csr, DMA_CH_CSR, BUSY );
|
CLEAR_FLAG( channel->regs.csr, DMA_CH_CSR, BUSY );
|
|
|
/* If needed, generate interrupt */
|
/* If needed, generate interrupt */
|
if ( generate_interrupt )
|
if ( generate_interrupt ) {
|
{
|
|
/* TODO: Which channel should we interrupt? */
|
/* TODO: Which channel should we interrupt? */
|
if ( TEST_FLAG( channel->regs.csr, DMA_CH_CSR, INE_DONE ) &&
|
if ( TEST_FLAG( channel->regs.csr, DMA_CH_CSR, INE_DONE ) &&
|
(channel->controller->regs.int_msk_a & channel->channel_mask) )
|
(channel->controller->regs.int_msk_a & channel->channel_mask) ) {
|
{
|
|
SET_FLAG( channel->regs.csr, DMA_CH_CSR, INT_DONE );
|
SET_FLAG( channel->regs.csr, DMA_CH_CSR, INT_DONE );
|
channel->controller->regs.int_src_a = channel->channel_mask;
|
channel->controller->regs.int_src_a = channel->channel_mask;
|
report_interrupt( INT_DMA );
|
report_interrupt( channel->controller->irq );
|
}
|
}
|
}
|
}
|
}
|
}
|
|
|
/* Utility function: Add 4 to a value with a mask */
|
/* Utility function: Add 4 to a value with a mask */
|
