| Line 31... |
Line 31... |
#define SPRGROUP_DMMU 0x01000000
|
#define SPRGROUP_DMMU 0x01000000
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#define SPRGROUP_IMMU 0x02000000
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#define SPRGROUP_IMMU 0x02000000
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#define SPRGROUP_DC 0x03000000
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#define SPRGROUP_DC 0x03000000
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#define SPRGROUP_IC 0x04000000
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#define SPRGROUP_IC 0x04000000
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#define SPRGROUP_MAC 0x05000000
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#define SPRGROUP_MAC 0x05000000
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#define SPRGROUP_TT 0x09000000
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#define SPRGROUP_D 0x06000000
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#define SPRGROUP_PC 0x07000000
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#define SPRGROUP_PM 0x08000000
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#define SPRGROUP_PIC 0x09000000
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#define SPRGROUP_TT 0x0A000000
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|
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/* System control and status group */
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/* System control and status group */
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#define SPR_VR (SPRGROUP_SYS + 0)
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#define SPR_VR (SPRGROUP_SYS + 0)
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#define SPR_MPR (SPRGROUP_SYS + 1)
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#define SPR_UPR (SPRGROUP_SYS + 1)
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#define SPR_SR (SPRGROUP_SYS + 2)
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#define SPR_SR (SPRGROUP_SYS + 2)
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#define SPR_EPCR_BASE (SPRGROUP_SYS + 16)
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#define SPR_EPCR_BASE (SPRGROUP_SYS + 16)
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#define SPR_EPCR_LAST (SPRGROUP_SYS + 31)
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#define SPR_EPCR_LAST (SPRGROUP_SYS + 31)
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#define SPR_CTR_BASE (SPRGROUP_SYS + 32)
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#define SPR_CTR_LAST (SPRGROUP_SYS + 47)
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#define SPR_EEAR_BASE (SPRGROUP_SYS + 48)
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#define SPR_EEAR_BASE (SPRGROUP_SYS + 48)
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#define SPR_EEAR_LAST (SPRGROUP_SYS + 63)
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#define SPR_EEAR_LAST (SPRGROUP_SYS + 63)
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#define SPR_ESR_BASE (SPRGROUP_SYS + 64)
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#define SPR_ESR_BASE (SPRGROUP_SYS + 64)
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#define SPR_ESR_LAST (SPRGROUP_SYS + 79)
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#define SPR_ESR_LAST (SPRGROUP_SYS + 79)
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| Line 62... |
Line 64... |
#define SPR_ITLBTR_BASE(WAY) (SPRGROUP_IMMU + 0x300 + (WAY) * 0x200)
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#define SPR_ITLBTR_BASE(WAY) (SPRGROUP_IMMU + 0x300 + (WAY) * 0x200)
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#define SPR_ITLBTR_LAST(WAY) (SPRGROUP_IMMU + 0x3ff + (WAY) * 0x200)
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#define SPR_ITLBTR_LAST(WAY) (SPRGROUP_IMMU + 0x3ff + (WAY) * 0x200)
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|
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/* Data cache group */
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/* Data cache group */
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#define SPR_DCCR (SPRGROUP_DC + 0)
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#define SPR_DCCR (SPRGROUP_DC + 0)
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#define SPR_DCBPR (SPRGROUP_DC + 1)
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#define SPR_DCBFR (SPRGROUP_DC + 2)
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#define SPR_DCBIR (SPRGROUP_DC + 3)
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#define SPR_DCBWR (SPRGROUP_DC + 4)
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#define SPR_DCBLR (SPRGROUP_DC + 5)
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#define SPR_DCR_BASE(WAY) (SPRGROUP_DC + 0x200 + (WAY) * 0x200)
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#define SPR_DCR_BASE(WAY) (SPRGROUP_DC + 0x200 + (WAY) * 0x200)
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#define SPR_DCR_LAST(WAY) (SPRGROUP_DC + 0x3ff + (WAY) * 0x200)
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#define SPR_DCR_LAST(WAY) (SPRGROUP_DC + 0x3ff + (WAY) * 0x200)
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/* Instruction cache group */
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/* Instruction cache group */
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#define SPR_ICCR (SPRGROUP_IC + 0)
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#define SPR_ICCR (SPRGROUP_IC + 0)
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#define SPR_ICBPR (SPRGROUP_IC + 1)
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#define SPR_ICBIR (SPRGROUP_IC + 2)
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#define SPR_ICBLR (SPRGROUP_IC + 3)
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#define SPR_ICR_BASE(WAY) (SPRGROUP_IC + 0x200 + (WAY) * 0x200)
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#define SPR_ICR_BASE(WAY) (SPRGROUP_IC + 0x200 + (WAY) * 0x200)
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#define SPR_ICR_LAST(WAY) (SPRGROUP_IC + 0x3ff + (WAY) * 0x200)
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#define SPR_ICR_LAST(WAY) (SPRGROUP_IC + 0x3ff + (WAY) * 0x200)
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/* MAC group */
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/* MAC group */
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#define SPR_MACLO (SPRGROUP_MAC + 1)
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#define SPR_MACLO (SPRGROUP_MAC + 1)
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#define SPR_MACHI (SPRGROUP_MAC + 2)
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#define SPR_MACHI (SPRGROUP_MAC + 2)
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/* Debug group */
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#define SPR_DVR(N) (SPRGROUP_D + (N))
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#define SPR_DCR(N) (SPRGROUP_D + 8 + (N))
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#define SPR_DMR1 (SPRGROUP_D + 16)
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#define SPR_DMR2 (SPRGROUP_D + 17)
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#define SPR_DWCR0 (SPRGROUP_D + 18)
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#define SPR_DWCR1 (SPRGROUP_D + 19)
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#define SPR_DSR (SPRGROUP_D + 20)
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#define SPR_DRR (SPRGROUP_D + 21)
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#define SPR_DIR (SPRGROUP_D + 22)
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|
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/* Performance counters group */
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#define SPR_PCCR(N) (SPRGROUP_PC + (N))
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#define SPR_PCMR(N) (SPRGROUP_PC + 8 + (N))
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/* Power management group */
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#define SPR_PMR (SPRGROUP_PM + 0)
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/* PIC group */
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#define SPR_PICMR (SPRGROUP_PIC + 0)
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#define SPR_PICPR (SPRGROUP_PIC + 1)
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#define SPR_PICSR (SPRGROUP_PIC + 2)
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/* Tick Timer group */
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/* Tick Timer group */
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#define SPR_TTCR (SPRGROUP_TT + 0)
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#define SPR_TTCR (SPRGROUP_TT + 0)
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#define SPR_TTIR (SPRGROUP_TT + 1)
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#define SPR_TTIR (SPRGROUP_TT + 1)
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|
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/*
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/*
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* Bit definitions for the Version Register
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* Bit definitions for the Version Register
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*
|
*
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*/
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*/
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#define SPR_VR_VER 0xffff0000 /* Processor version */
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#define SPR_VR_VER 0xffff0000 /* Processor version */
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#define SPR_VR_PT 0x0000f000 /* Predefined template */
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#define SPR_VR_REV 0x0000003f /* Processor revision */
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#define SPR_VR_REV 0x0000003f /* Processor revision */
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|
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/*
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/*
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* Bit definitions for the Module Present Register
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* Bit definitions for the Unit Present Register
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*
|
*
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*/
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*/
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#define SPR_MPR_SYS 0x00000001 /* System control and status module */
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#define SPR_UPR_UP 0x00000001 /* UPR present */
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#define SPR_MPR_DMMU 0x00000002 /* Data MMU module */
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#define SPR_UPR_DCP 0x00000002 /* Data cache present */
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#define SPR_MPR_IMMU 0x00000004 /* Instruction MMU module */
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#define SPR_UPR_ICP 0x00000004 /* Instruction cache present */
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#define SPR_MPR_DC 0x00000008 /* Data cache module */
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#define SPR_UPR_DMP 0x00000008 /* Data MMU present */
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#define SPR_MPR_IC 0x00000010 /* Instruction cache module */
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#define SPR_UPR_IMP 0x00000010 /* Instruction MMU present */
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#define SPR_MPR_MAC 0x00000020 /* MAC module */
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#define SPR_UPR_OB32P 0x00000020 /* ORBIS32 present */
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#define SPR_MPR_RES 0xffffffc0 /* Custom and future modules */
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#define SPR_UPR_OB64P 0x00000040 /* ORBIS64 present */
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#define SPR_UPR_OF32P 0x00000080 /* ORFPX32 present */
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#define SPR_UPR_OF64P 0x00000100 /* ORFPX64 present */
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#define SPR_UPR_OV32P 0x00000200 /* ORVDX32 present */
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#define SPR_UPR_OV64P 0x00000400 /* ORVDX64 present */
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#define SPR_UPR_DUP 0x00000800 /* Debug unit present */
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#define SPR_UPR_PCUP 0x00001000 /* Performance counters unit present */
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#define SPR_UPR_PMP 0x00002000 /* Power management present */
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#define SPR_UPR_PICP 0x00004000 /* PIC present */
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#define SPR_UPR_TTP 0x00008000 /* Tick timer present */
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#define SPR_UPR_SRP 0x00010000 /* Shadow registers present */
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#define SPR_UPR_RES 0x00fe0000 /* ORVDX32 present */
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#define SPR_UPR_CUST 0xff000000 /* Custom units */
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/*
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/*
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* Bit definitions for the Supervision Register
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* Bit definitions for the Supervision Register
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*
|
*
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*/
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*/
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#define SPR_SR_CID 0xf0000000 /* Context ID */
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#define SPR_SR_CID 0xf0000000 /* Context ID */
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#define SPR_SR_CF 0x00000100 /* Condition Flag */
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#define SPR_SR_PXR 0x00008000 /* Partial exception recognition */
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#define SPR_SR_EP 0x00004000 /* Exception Prefix */
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#define SPR_SR_DSX 0x00002000 /* Delay Slot Exception */
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#define SPR_SR_OVE 0x00001000 /* Overflow flag Exception */
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#define SPR_SR_OV 0x00000800 /* Overflow flag */
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#define SPR_SR_CY 0x00000400 /* Carry flag */
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#define SPR_SR_F 0x00000200 /* Condition Flag */
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#define SPR_SR_CE 0x00000100 /* CID Enable */
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#define SPR_SR_LEE 0x00000080 /* Little Endian Enable */
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#define SPR_SR_LEE 0x00000080 /* Little Endian Enable */
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#define SPR_SR_IME 0x00000040 /* Instruction MMU Enable */
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#define SPR_SR_IME 0x00000040 /* Instruction MMU Enable */
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#define SPR_SR_DME 0x00000020 /* Data MMU Enable */
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#define SPR_SR_DME 0x00000020 /* Data MMU Enable */
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#define SPR_SR_ICE 0x00000010 /* Instruction Cache Enable */
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#define SPR_SR_ICE 0x00000010 /* Instruction Cache Enable */
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#define SPR_SR_DCE 0x00000008 /* Data Cache Enable */
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#define SPR_SR_DCE 0x00000008 /* Data Cache Enable */
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#define SPR_SR_EIR 0x00000004 /* External Interrupt Recognition */
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#define SPR_SR_EIR 0x00000004 /* External Interrupt Recognition */
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#define SPR_SR_EXR 0x00000002 /* Exception Recognition */
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#define SPR_SR_EXR 0x00000002 /* Exception Recognition */
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#define SPR_SR_SUPV 0x00000001 /* Supervisor mode */
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#define SPR_SR_SUPV 0x00000001 /* Supervisor mode */
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|
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/*
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/*
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* Bit definitions for the Condition Code Register
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*
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*/
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#define SPR_CCR_OVERFL 0x00000004 /* Overflow */
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#define SPR_CCR_CARRY 0x00000002 /* Carry */
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#define SPR_CCR_FLAG 0x00000001 /* Compare Flag */
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/*
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* Bit definitions for the Data MMU Control Register
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* Bit definitions for the Data MMU Control Register
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*
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*
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*/
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*/
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#define SPR_DMMUCR_P2S 0x0000003e /* Level 2 Page Size */
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#define SPR_DMMUCR_P2S 0x0000003e /* Level 2 Page Size */
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#define SPR_DMMUCR_P1S 0x000007c0 /* Level 1 Page Size */
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#define SPR_DMMUCR_P1S 0x000007c0 /* Level 1 Page Size */
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| Line 192... |
Line 235... |
#define SPR_ITLBTR_SRE 0x00000100 /* Supervisor Read Enable */
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#define SPR_ITLBTR_SRE 0x00000100 /* Supervisor Read Enable */
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#define SPR_ITLBTR_SWE 0x00000200 /* Supervisor Write Enable (not used actually) */
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#define SPR_ITLBTR_SWE 0x00000200 /* Supervisor Write Enable (not used actually) */
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#define SPR_ITLBTR_PPN 0xfffff000 /* Physical Page Number */
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#define SPR_ITLBTR_PPN 0xfffff000 /* Physical Page Number */
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/*
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/*
|
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* Bit definitions for Data Cache Control register
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|
*
|
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*/
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#define SPR_DCCR_EW 0x000000ff /* Enable ways */
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|
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/*
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* Bit definitions for Insn Cache Control register
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*
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*/
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#define SPR_ICCR_EW 0x000000ff /* Enable ways */
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|
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/*
|
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* Bit definitions for Debug Control registers
|
|
*
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*/
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#define SPR_DCR_DP 0x00000001 /* DVR/DCR present */
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#define SPR_DCR_CC 0x0000000e /* Compare condition */
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#define SPR_DCR_SC 0x00000010 /* Signed compare */
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#define SPR_DCR_CT 0x000000e0 /* Compare to */
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|
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/*
|
|
* Bit definitions for Debug Mode 1 register
|
|
*
|
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*/
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#define SPR_DMR1_CW0 0x00000003 /* Chain watchpoint 0 */
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#define SPR_DMR1_CW1 0x0000000c /* Chain watchpoint 1 */
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#define SPR_DMR1_CW2 0x00000030 /* Chain watchpoint 2 */
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#define SPR_DMR1_CW3 0x000000c0 /* Chain watchpoint 3 */
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#define SPR_DMR1_CW4 0x00000300 /* Chain watchpoint 4 */
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#define SPR_DMR1_CW5 0x00000c00 /* Chain watchpoint 5 */
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#define SPR_DMR1_CW6 0x00003000 /* Chain watchpoint 6 */
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#define SPR_DMR1_CW7 0x0000c000 /* Chain watchpoint 7 */
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#define SPR_DMR1_CW8 0x00030000 /* Chain watchpoint 8 */
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#define SPR_DMR1_CW9 0x000c0000 /* Chain watchpoint 9 */
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#define SPR_DMR1_CW10 0x00300000 /* Chain watchpoint 10 */
|
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#define SPR_DMR1_ST 0x00400000 /* Single-step trace*/
|
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#define SPR_DMR1_BT 0x00800000 /* Branch trace */
|
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#define SPR_DMR1_DXFW 0x01000000 /* Disable external force watchpoint */
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|
|
|
/*
|
|
* Bit definitions for Debug Mode 2 register
|
|
*
|
|
*/
|
|
#define SPR_DMR2_WCE0 0x00000001 /* Watchpoint counter 0 enable */
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#define SPR_DMR2_WCE1 0x00000002 /* Watchpoint counter 0 enable */
|
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#define SPR_DMR2_AWTC 0x00001ffc /* Assign watchpoints to counters */
|
|
#define SPR_DMR2_WGB 0x00ffe000 /* Watchpoints generating breakpoint */
|
|
|
|
/*
|
|
* Bit definitions for Debug watchpoint counter registers
|
|
*
|
|
*/
|
|
#define SPR_DWCR_COUNT 0x0000ffff /* Count */
|
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#define SPR_DWCR_MATCH 0xffff0000 /* Match */
|
|
|
|
/*
|
|
* Bit definitions for Debug stop register
|
|
*
|
|
*/
|
|
#define SPR_DSR_RSTE 0x00000001 /* Reset exception */
|
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#define SPR_DSR_BUSEE 0x00000002 /* Bus error exception */
|
|
#define SPR_DSR_DPFE 0x00000004 /* Data Page Fault exception */
|
|
#define SPR_DSR_IPFE 0x00000008 /* Insn Page Fault exception */
|
|
#define SPR_DSR_LPINTE 0x00000010 /* Low priority interrupt exception */
|
|
#define SPR_DSR_AE 0x00000020 /* Alignment exception */
|
|
#define SPR_DSR_IIE 0x00000040 /* Illegal Instruction exception */
|
|
#define SPR_DSR_HPINTE 0x00000080 /* High priority interrupt exception */
|
|
#define SPR_DSR_DME 0x00000100 /* DTLB miss exception */
|
|
#define SPR_DSR_IME 0x00000200 /* ITLB miss exception */
|
|
#define SPR_DSR_RE 0x00000400 /* Range exception */
|
|
#define SPR_DSR_SCE 0x00000800 /* System call exception */
|
|
#define SPR_DSR_BE 0x00001000 /* Breakpoint exception */
|
|
|
|
/*
|
|
* Bit definitions for Debug reason register
|
|
*
|
|
*/
|
|
#define SPR_DRR_RSTE 0x00000001 /* Reset exception */
|
|
#define SPR_DRR_BUSEE 0x00000002 /* Bus error exception */
|
|
#define SPR_DRR_DPFE 0x00000004 /* Data Page Fault exception */
|
|
#define SPR_DRR_IPFE 0x00000008 /* Insn Page Fault exception */
|
|
#define SPR_DRR_LPINTE 0x00000010 /* Low priority interrupt exception */
|
|
#define SPR_DRR_AE 0x00000020 /* Alignment exception */
|
|
#define SPR_DRR_IIE 0x00000040 /* Illegal Instruction exception */
|
|
#define SPR_DRR_HPINTE 0x00000080 /* High priority interrupt exception */
|
|
#define SPR_DRR_DME 0x00000100 /* DTLB miss exception */
|
|
#define SPR_DRR_IME 0x00000200 /* ITLB miss exception */
|
|
#define SPR_DRR_RE 0x00000400 /* Range exception */
|
|
#define SPR_DRR_SCE 0x00000800 /* System call exception */
|
|
#define SPR_DRR_BE 0x00001000 /* Breakpoint exception */
|
|
|
|
/*
|
|
* Bit definitions for Performance counters mode registers
|
|
*
|
|
*/
|
|
#define SPR_PCMR_CP 0x00000001 /* Counter present */
|
|
#define SPR_PCMR_UMRA 0x00000002 /* User mode read access */
|
|
#define SPR_PCMR_CISM 0x00000004 /* Count in supervisor mode */
|
|
#define SPR_PCMR_CIUM 0x00000008 /* Count in user mode */
|
|
#define SPR_PCMR_LA 0x00000010 /* Load access event */
|
|
#define SPR_PCMR_SA 0x00000020 /* Store access event */
|
|
#define SPR_PCMR_IF 0x00000040 /* Instruction fetch event*/
|
|
#define SPR_PCMR_DCM 0x00000080 /* Data cache miss event */
|
|
#define SPR_PCMR_ICM 0x00000100 /* Insn cache miss event */
|
|
#define SPR_PCMR_IFS 0x00000200 /* Insn fetch stall event */
|
|
#define SPR_PCMR_LSUS 0x00000400 /* LSU stall event */
|
|
#define SPR_PCMR_BS 0x00000800 /* Branch stall event */
|
|
#define SPR_PCMR_DTLBM 0x00001000 /* DTLB miss event */
|
|
#define SPR_PCMR_ITLBM 0x00002000 /* ITLB miss event */
|
|
#define SPR_PCMR_DDS 0x00004000 /* Data dependency stall event */
|
|
#define SPR_PCMR_WPE 0x03ff8000 /* Watchpoint events */
|
|
|
|
/*
|
|
* Bit definitions for the Power management register
|
|
*
|
|
*/
|
|
#define SPR_PMR_SDF 0x00000001 /* Slow down factor */
|
|
#define SPR_PMR_DME 0x00000002 /* Doze mode enable */
|
|
#define SPR_PMR_SME 0x00000004 /* Sleep mode enable */
|
|
#define SPR_PMR_DCGE 0x00000008 /* Dynamic clock gating enable */
|
|
#define SPR_PMR_SUME 0x00000010 /* Suspend mode enable */
|
|
|
|
/*
|
|
* Bit definitions for PICMR
|
|
*
|
|
*/
|
|
#define SPR_PICMR_IUM 0xfffffffc /* Interrupt unmask */
|
|
|
|
/*
|
|
* Bit definitions for PICPR
|
|
*
|
|
*/
|
|
#define SPR_PICPR_IPRIO 0xfffffffc /* Interrupt priority */
|
|
|
|
/*
|
|
* Bit definitions for PICSR
|
|
*
|
|
*/
|
|
#define SPR_PICSR_IS 0xffffffff /* Interrupt status */
|
|
|
|
/*
|
* Bit definitions for Tick Timer Control Register
|
* Bit definitions for Tick Timer Control Register
|
*
|
*
|
*/
|
*/
|
#define SPR_TTCR_PERIOD 0x0fffffff /* Time Period */
|
#define SPR_TTCR_PERIOD 0x0fffffff /* Time Period */
|
#define SPR_TTCR_IP 0x10000000 /* Interrupt Present */
|
#define SPR_TTCR_IP 0x10000000 /* Interrupt Present */
|
