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Line 31... |
#include "dcache_model.h"
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#include "dcache_model.h"
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#include "abstract.h"
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#include "abstract.h"
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#include "stats.h"
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#include "stats.h"
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#include "spr_defs.h"
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#include "spr_defs.h"
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#include "sprs.h"
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#include "sprs.h"
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#include "sim-config.h"
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/* Data cache */
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/* Data cache */
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/* Number of DC sets (power of 2) */
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#define DC_SETS 512
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/* Block size in bytes (1, 2, 4, 8, 16, 32 etc.) */
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#define DC_BLOCK_SIZE 16
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/* Number of DC ways (1, 2, 3 etc.). */
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#define DC_WAYS 1
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/* Number of usage states (2, 3, 4 etc.). */
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#define DC_USTATES 2
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struct dc_set {
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struct dc_set {
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struct {
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struct {
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unsigned long tagaddr; /* tag address */
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unsigned long tagaddr; /* tag address */
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int lru; /* least recently used */
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int lru; /* least recently used */
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} way[DC_WAYS];
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} way[MAX_DC_WAYS];
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} dc[DC_SETS];
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} dc[MAX_DC_SETS];
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void dc_info()
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void dc_info()
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{
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{
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if (!testsprbits(SPR_UPR, SPR_UPR_DCP)) {
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if (!testsprbits(SPR_UPR, SPR_UPR_DCP)) {
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printf("DCache not implemented. Set UPR[DCP].\n");
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printf("DCache not implemented. Set UPR[DCP].\n");
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return;
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return;
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}
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}
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printf("Data cache %dKB: ", DC_SETS * DC_BLOCK_SIZE * DC_WAYS / 1024);
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printf("Data cache %dKB: ", config.dc.nsets * config.dc.blocksize * config.dc.nways / 1024);
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printf("%d ways, %d sets, block size %d bytes\n", DC_WAYS, DC_SETS, DC_BLOCK_SIZE);
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printf("%d ways, %d sets, block size %d bytes\n", config.dc.nways, config.dc.nsets, config.dc.blocksize);
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}
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}
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/* First check if data is already in the cache and if it is:
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/* First check if data is already in the cache and if it is:
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- increment DC read hit stats,
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- increment DC read hit stats,
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- set 'lru' at this way to DC_USTATES - 1 and
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- set 'lru' at this way to config.dc.ustates - 1 and
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decrement 'lru' of other ways unless they have reached 0,
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decrement 'lru' of other ways unless they have reached 0,
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and if not:
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and if not:
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- increment DC read miss stats
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- increment DC read miss stats
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- find lru way and entry and replace old tag with tag of the 'dataaddr'
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- find lru way and entry and replace old tag with tag of the 'dataaddr'
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- set 'lru' with DC_USTATES - 1 and decrement 'lru' of other
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- set 'lru' with config.dc.ustates - 1 and decrement 'lru' of other
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ways unless they have reached 0
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ways unless they have reached 0
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*/
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*/
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void dc_simulate_read(unsigned long dataaddr)
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void dc_simulate_read(unsigned long dataaddr)
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{
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{
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Line 85... |
Line 74... |
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if ((!testsprbits(SPR_UPR, SPR_UPR_DCP)) || (!testsprbits(SPR_SR, SPR_SR_DCE)))
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if ((!testsprbits(SPR_UPR, SPR_UPR_DCP)) || (!testsprbits(SPR_SR, SPR_SR_DCE)))
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return;
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return;
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/* Which set to check out? */
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/* Which set to check out? */
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set = (dataaddr / DC_BLOCK_SIZE) % DC_SETS;
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set = (dataaddr / config.dc.blocksize) % config.dc.nsets;
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tagaddr = (dataaddr / DC_BLOCK_SIZE) / DC_SETS;
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tagaddr = (dataaddr / config.dc.blocksize) / config.dc.nsets;
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/* Scan all ways and try to find a matching way. */
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/* Scan all ways and try to find a matching way. */
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for (i = 0; i < DC_WAYS; i++)
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for (i = 0; i < config.dc.nways; i++)
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if (dc[set].way[i].tagaddr == tagaddr)
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if (dc[set].way[i].tagaddr == tagaddr)
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way = i;
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way = i;
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/* Did we find our cached data? */
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/* Did we find our cached data? */
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if (way >= 0) { /* Yes, we did. */
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if (way >= 0) { /* Yes, we did. */
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dc_stats.readhit++;
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dc_stats.readhit++;
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for (i = 0; i < DC_WAYS; i++)
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for (i = 0; i < config.dc.nways; i++)
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if (dc[set].way[i].lru)
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if (dc[set].way[i].lru)
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dc[set].way[i].lru--;
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dc[set].way[i].lru--;
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dc[set].way[way].lru = DC_USTATES - 1;
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dc[set].way[way].lru = config.dc.ustates - 1;
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}
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}
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else { /* No, we didn't. */
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else { /* No, we didn't. */
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int minlru = DC_USTATES - 1;
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int minlru = config.dc.ustates - 1;
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int minway = 0;
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int minway = 0;
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dc_stats.readmiss++;
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dc_stats.readmiss++;
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for (i = 0; i < DC_WAYS; i++)
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for (i = 0; i < config.dc.nways; i++)
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if ((dc[set].way[i].lru < minlru) &&
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if ((dc[set].way[i].lru < minlru) &&
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(getsprbits(SPR_DCCR, SPR_DCCR_EW) & (1 << i)))
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(getsprbits(SPR_DCCR, SPR_DCCR_EW) & (1 << i)))
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minway = i;
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minway = i;
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dc[set].way[minway].tagaddr = tagaddr;
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dc[set].way[minway].tagaddr = tagaddr;
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for (i = 0; i < DC_WAYS; i++)
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for (i = 0; i < config.dc.nways; i++)
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if (dc[set].way[i].lru)
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if (dc[set].way[i].lru)
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dc[set].way[i].lru--;
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dc[set].way[i].lru--;
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dc[set].way[minway].lru = DC_USTATES - 1;
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dc[set].way[minway].lru = config.dc.ustates - 1;
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}
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}
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}
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}
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/* First check if data is already in the cache and if it is:
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/* First check if data is already in the cache and if it is:
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- increment DC write hit stats,
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- increment DC write hit stats,
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- set 'lru' at this way to DC_USTATES - 1 and
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- set 'lru' at this way to config.dc.ustates - 1 and
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decrement 'lru' of other ways unless they have reached 0,
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decrement 'lru' of other ways unless they have reached 0,
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and if not:
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and if not:
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- increment DC write miss stats
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- increment DC write miss stats
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- find lru way and entry and replace old tag with tag of the 'dataaddr'
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- find lru way and entry and replace old tag with tag of the 'dataaddr'
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- set 'lru' with DC_USTATES - 1 and decrement 'lru' of other
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- set 'lru' with config.dc.ustates - 1 and decrement 'lru' of other
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ways unless they have reached 0
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ways unless they have reached 0
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*/
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*/
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void dc_simulate_write(unsigned long dataaddr)
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void dc_simulate_write(unsigned long dataaddr)
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{
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{
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Line 142... |
Line 131... |
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if ((!testsprbits(SPR_UPR, SPR_UPR_DCP)) || (!testsprbits(SPR_SR, SPR_SR_DCE)))
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if ((!testsprbits(SPR_UPR, SPR_UPR_DCP)) || (!testsprbits(SPR_SR, SPR_SR_DCE)))
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return;
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return;
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/* Which set to check out? */
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/* Which set to check out? */
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set = (dataaddr / DC_BLOCK_SIZE) % DC_SETS;
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set = (dataaddr / config.dc.blocksize) % config.dc.nsets;
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tagaddr = (dataaddr / DC_BLOCK_SIZE) / DC_SETS;
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tagaddr = (dataaddr / config.dc.blocksize) / config.dc.nsets;
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/* Scan all ways and try to find a matching way. */
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/* Scan all ways and try to find a matching way. */
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for (i = 0; i < DC_WAYS; i++)
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for (i = 0; i < config.dc.nways; i++)
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if (dc[set].way[i].tagaddr == tagaddr)
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if (dc[set].way[i].tagaddr == tagaddr)
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way = i;
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way = i;
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/* Did we find our cached data? */
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/* Did we find our cached data? */
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if (way >= 0) { /* Yes, we did. */
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if (way >= 0) { /* Yes, we did. */
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dc_stats.writehit++;
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dc_stats.writehit++;
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for (i = 0; i < DC_WAYS; i++)
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for (i = 0; i < config.dc.nways; i++)
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if (dc[set].way[i].lru)
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if (dc[set].way[i].lru)
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dc[set].way[i].lru--;
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dc[set].way[i].lru--;
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dc[set].way[way].lru = DC_USTATES - 1;
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dc[set].way[way].lru = config.dc.ustates - 1;
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}
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}
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else { /* No, we didn't. */
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else { /* No, we didn't. */
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int minlru = DC_USTATES - 1;
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int minlru = config.dc.ustates - 1;
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int minway = 0;
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int minway = 0;
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dc_stats.writemiss++;
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dc_stats.writemiss++;
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for (i = 0; i < DC_WAYS; i++)
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for (i = 0; i < config.dc.nways; i++)
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if ((dc[set].way[i].lru < minlru) &&
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if ((dc[set].way[i].lru < minlru) &&
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(getsprbits(SPR_DCCR, SPR_DCCR_EW) & (1 << i)))
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(getsprbits(SPR_DCCR, SPR_DCCR_EW) & (1 << i)))
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minway = i;
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minway = i;
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dc[set].way[minway].tagaddr = tagaddr;
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dc[set].way[minway].tagaddr = tagaddr;
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for (i = 0; i < DC_WAYS; i++)
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for (i = 0; i < config.dc.nways; i++)
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if (dc[set].way[i].lru)
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if (dc[set].way[i].lru)
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dc[set].way[i].lru--;
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dc[set].way[i].lru--;
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dc[set].way[minway].lru = DC_USTATES - 1;
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dc[set].way[minway].lru = config.dc.ustates - 1;
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}
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}
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}
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}
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/* First check if data is already in the cache and if it is:
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/* First check if data is already in the cache and if it is:
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- invalidate block if way isn't locked
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- invalidate block if way isn't locked
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Line 193... |
Line 182... |
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if (!testsprbits(SPR_UPR, SPR_UPR_DCP))
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if (!testsprbits(SPR_UPR, SPR_UPR_DCP))
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return;
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return;
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/* Which set to check out? */
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/* Which set to check out? */
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set = (dataaddr / DC_BLOCK_SIZE) % DC_SETS;
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set = (dataaddr / config.dc.blocksize) % config.dc.nsets;
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tagaddr = (dataaddr / DC_BLOCK_SIZE) / DC_SETS;
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tagaddr = (dataaddr / config.dc.blocksize) / config.dc.nsets;
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/* Scan all ways and try to find a matching way. */
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/* Scan all ways and try to find a matching way. */
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for (i = 0; i < DC_WAYS; i++)
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for (i = 0; i < config.dc.nways; i++)
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if (dc[set].way[i].tagaddr == tagaddr)
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if (dc[set].way[i].tagaddr == tagaddr)
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way = i;
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way = i;
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/* Did we find our cached data? */
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/* Did we find our cached data? */
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if ((way >= 0) && (getsprbits(SPR_DCCR, SPR_DCCR_EW) & (1 << way))) { /* Yes, we did. */
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if ((way >= 0) && (getsprbits(SPR_DCCR, SPR_DCCR_EW) & (1 << way))) { /* Yes, we did. */
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