| Line 38... |
Line 38... |
#include "stats.h"
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#include "stats.h"
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#include "except.h"
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#include "except.h"
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#include "sprs.h"
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#include "sprs.h"
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#include "sim-config.h"
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#include "sim-config.h"
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#include "debug_unit.h"
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#include "debug_unit.h"
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#include "opcode/or32.h"
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#include "immu.h"
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#include "dmmu.h"
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#include "debug.h"
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|
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/* General purpose registers. */
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/* General purpose registers. */
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machword reg[MAX_GPRS];
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machword reg[MAX_GPRS];
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|
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/* Instruction queue */
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/* Instruction queue */
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| Line 215... |
Line 219... |
/* We search all source operands - if we find confict => return 1 */
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/* We search all source operands - if we find confict => return 1 */
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i = 0;
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i = 0;
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while (!(next->op[i + MAX_OPERANDS] & OPTYPE_LAST))
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while (!(next->op[i + MAX_OPERANDS] & OPTYPE_LAST))
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if (!(next->op[i + MAX_OPERANDS] & OPTYPE_DST))
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if (!(next->op[i + MAX_OPERANDS] & OPTYPE_DST))
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{
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{
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if (next->op[i + MAX_OPERANDS] & OPTYPE_DIS)
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if (next->op[i + MAX_OPERANDS] & OPTYPE_DIS) {
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if (type & OPTYPE_DIS)
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if (type & OPTYPE_DIS)
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return 1;
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return 1;
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else if (next->op[i] == prev->op[i]
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else if (next->op[i] == prev->op[i]
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&& (next->op[i + MAX_OPERANDS] & OPTYPE_REG))
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&& (next->op[i + MAX_OPERANDS] & OPTYPE_REG))
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return 1;
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return 1;
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}
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if (next->op[i] == prev->op[i]
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if (next->op[i] == prev->op[i]
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&& (next->op[i + MAX_OPERANDS] & OPTYPE_REG)
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&& (next->op[i + MAX_OPERANDS] & OPTYPE_REG)
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&& (type & OPTYPE_REG))
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&& (type & OPTYPE_REG))
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return 1;
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return 1;
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i++;
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i++;
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| Line 244... |
Line 249... |
|
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/* Modified by CZ 26/05/01 for new mode execution */
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/* Modified by CZ 26/05/01 for new mode execution */
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/* Fetch returns nonzero if instruction should NOT be executed. */
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/* Fetch returns nonzero if instruction should NOT be executed. */
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static inline int fetch()
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static inline int fetch()
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{
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{
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struct mem_entry *entry;
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|
|
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/* Update the pc for pending exceptions, or get physical pc */
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/* Update the pc for pending exceptions, or get physical pc */
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if (!pending.valid)
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if (!pending.valid)
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pc_phy = immu_translate(pc, 0);
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pc_phy = immu_translate(pc);
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|
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if(pending.valid)
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if(pending.valid)
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except_handle_backend(pending.type, pending.address, pending.saved);
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except_handle_backend(pending.type, pending.address, pending.saved);
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|
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if (CHECK_BREAKPOINTS) {
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if (CHECK_BREAKPOINTS) {
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| Line 360... |
Line 363... |
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if (config.sim.exe_log) dump_exe_log();
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if (config.sim.exe_log) dump_exe_log();
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}
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}
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|
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/* Store buffer analysis - stores are accumulated and commited when IO is idle */
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/* Store buffer analysis - stores are accumulated and commited when IO is idle */
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static inline sbuf_store (int cyc) {
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static inline void sbuf_store (int cyc) {
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int delta = runtime.sim.cycles - sbuf_prev_cycles;
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int delta = runtime.sim.cycles - sbuf_prev_cycles;
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sbuf_total_cyc += cyc;
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sbuf_total_cyc += cyc;
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sbuf_prev_cycles = runtime.sim.cycles;
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sbuf_prev_cycles = runtime.sim.cycles;
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|
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//PRINTF (">STORE %i,%i,%i,%i,%i\n", delta, sbuf_count, sbuf_tail, sbuf_head, sbuf_buf[sbuf_tail], sbuf_buf[sbuf_head]);
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//PRINTF (">STORE %i,%i,%i,%i,%i\n", delta, sbuf_count, sbuf_tail, sbuf_head, sbuf_buf[sbuf_tail], sbuf_buf[sbuf_head]);
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| Line 392... |
Line 395... |
sbuf_count++;
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sbuf_count++;
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//PRINTF ("|STORE %i,%i,%i,%i,%i\n", delta, sbuf_count, sbuf_tail, sbuf_head, sbuf_buf[sbuf_tail], sbuf_buf[sbuf_head]);
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//PRINTF ("|STORE %i,%i,%i,%i,%i\n", delta, sbuf_count, sbuf_tail, sbuf_head, sbuf_buf[sbuf_tail], sbuf_buf[sbuf_head]);
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}
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}
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|
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/* Store buffer analysis - previous stores should commit, before any load */
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/* Store buffer analysis - previous stores should commit, before any load */
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static inline sbuf_load () {
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static inline void sbuf_load () {
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int delta = runtime.sim.cycles - sbuf_prev_cycles;
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int delta = runtime.sim.cycles - sbuf_prev_cycles;
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sbuf_prev_cycles = runtime.sim.cycles;
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sbuf_prev_cycles = runtime.sim.cycles;
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|
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//PRINTF (">LOAD %i,%i,%i,%i,%i\n", delta, sbuf_count, sbuf_tail, sbuf_head, sbuf_buf[sbuf_tail], sbuf_buf[sbuf_head]);
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//PRINTF (">LOAD %i,%i,%i,%i,%i\n", delta, sbuf_count, sbuf_tail, sbuf_head, sbuf_buf[sbuf_tail], sbuf_buf[sbuf_head]);
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//PRINTF ("|%i,%i\n", sbuf_total_cyc, sbuf_wait_cyc);
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//PRINTF ("|%i,%i\n", sbuf_total_cyc, sbuf_wait_cyc);
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| Line 430... |
Line 433... |
if (config.sim.exe_log_marker && runtime.cpu.instructions % config.sim.exe_log_marker == 0) {
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if (config.sim.exe_log_marker && runtime.cpu.instructions % config.sim.exe_log_marker == 0) {
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fprintf (runtime.sim.fexe_log, "--------------------- %8i instruction ---------------------\n", runtime.cpu.instructions);
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fprintf (runtime.sim.fexe_log, "--------------------- %8i instruction ---------------------\n", runtime.cpu.instructions);
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}
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}
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switch (config.sim.exe_log_type) {
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switch (config.sim.exe_log_type) {
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case EXE_LOG_HARDWARE:
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case EXE_LOG_HARDWARE:
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fprintf (runtime.sim.fexe_log, "\nEXECUTED(%11lu): %.8lx: ", runtime.cpu.instructions, i);
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fprintf (runtime.sim.fexe_log, "\nEXECUTED(%11u): %.8lx: ", runtime.cpu.instructions, i);
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fprintf (runtime.sim.fexe_log, "%.2x%.2x", evalsim_mem8(i), evalsim_mem8(i + 1));
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fprintf (runtime.sim.fexe_log, "%.2x%.2x", evalsim_mem8(i), evalsim_mem8(i + 1));
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fprintf (runtime.sim.fexe_log, "%.2x%.2x", evalsim_mem8(i + 2), evalsim_mem8(i + 3));
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fprintf (runtime.sim.fexe_log, "%.2x%.2x", evalsim_mem8(i + 2), evalsim_mem8(i + 3));
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for(i = 0; i < MAX_GPRS; i++) {
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for(i = 0; i < MAX_GPRS; i++) {
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if (i % 4 == 0)
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if (i % 4 == 0)
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fprintf(runtime.sim.fexe_log, "\n");
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fprintf(runtime.sim.fexe_log, "\n");
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fprintf (runtime.sim.fexe_log, "GPR%2u: %.8lx ", i, reg[i]);
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fprintf (runtime.sim.fexe_log, "GPR%2lu: %.8lx ", i, reg[i]);
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}
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}
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fprintf (runtime.sim.fexe_log, "\n");
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fprintf (runtime.sim.fexe_log, "\n");
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fprintf (runtime.sim.fexe_log, "SR : %.8lx ", mfspr(SPR_SR));
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fprintf (runtime.sim.fexe_log, "SR : %.8lx ", mfspr(SPR_SR));
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fprintf (runtime.sim.fexe_log, "EPCR0: %.8lx ", mfspr(SPR_EPCR_BASE));
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fprintf (runtime.sim.fexe_log, "EPCR0: %.8lx ", mfspr(SPR_EPCR_BASE));
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fprintf (runtime.sim.fexe_log, "EEAR0: %.8lx ", mfspr(SPR_EEAR_BASE));
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fprintf (runtime.sim.fexe_log, "EEAR0: %.8lx ", mfspr(SPR_EEAR_BASE));
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| Line 462... |
Line 465... |
int i,j=0;
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int i,j=0;
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|
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for (i = 0; i < num_op; i++)
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for (i = 0; i < num_op; i++)
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if (op[i + MAX_OPERANDS] & OPTYPE_DIS) {
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if (op[i + MAX_OPERANDS] & OPTYPE_DIS) {
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j=1;
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j=1;
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fprintf (runtime.sim.fexe_log, "EA =%08x PA =%08x ", op[i], dmmu_translate(op[i],0));
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fprintf (runtime.sim.fexe_log, "EA =%08lx PA =%08lx ", op[i],
|
|
dmmu_translate(op[i],0));
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} else if ((op[i + MAX_OPERANDS] & OPTYPE_REG) && op[i]) {
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} else if ((op[i + MAX_OPERANDS] & OPTYPE_REG) && op[i]) {
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fprintf (runtime.sim.fexe_log, "r%-2i=%08x ", op[i], evalsim_reg32 (op[i]));
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fprintf (runtime.sim.fexe_log, "r%-2li=%08lx ", op[i],
|
|
evalsim_reg32 (op[i]));
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} else
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} else
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fprintf (runtime.sim.fexe_log, " ");
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fprintf (runtime.sim.fexe_log, " ");
|
|
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i+=j;
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i+=j;
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for (; i < 3; i++)
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for (; i < 3; i++)
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| Line 484... |
Line 489... |
/* Dump registers - 'r' or 't' command */
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/* Dump registers - 'r' or 't' command */
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void dumpreg()
|
void dumpreg()
|
{
|
{
|
int i;
|
int i;
|
char temp[100];
|
char temp[100];
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unsigned int physical_pc;
|
unsigned long physical_pc;
|
|
|
if (physical_pc = peek_into_itlb(iqueue[0].insn_addr)) {
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if ((physical_pc = peek_into_itlb(iqueue[0].insn_addr))) {
|
/*
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/*
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* PRINTF("\t\t\tEA: %08x <--> PA: %08x\n", iqueue[0].insn_addr, physical_pc);
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* PRINTF("\t\t\tEA: %08x <--> PA: %08x\n", iqueue[0].insn_addr, physical_pc);
|
*/
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*/
|
dumpmemory(physical_pc, physical_pc + 4, 1, 0);
|
dumpmemory(physical_pc, physical_pc + 4, 1, 0);
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}
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}
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| Line 507... |
Line 512... |
PRINTF (" HAZARDWAIT: %u\n", runtime.cpu.hazardwait);
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PRINTF (" HAZARDWAIT: %u\n", runtime.cpu.hazardwait);
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else
|
else
|
if (config.cpu.superscalar)
|
if (config.cpu.superscalar)
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PRINTF ("\n");
|
PRINTF ("\n");
|
|
|
if (physical_pc = peek_into_itlb(pc)) {
|
if ((physical_pc = peek_into_itlb(pc))) {
|
/*
|
/*
|
* PRINTF("\t\t\tEA: %08x <--> PA: %08x\n", pc, physical_pc);
|
* PRINTF("\t\t\tEA: %08x <--> PA: %08x\n", pc, physical_pc);
|
*/
|
*/
|
dumpmemory(physical_pc, physical_pc + 4, 1, 0);
|
dumpmemory(physical_pc, physical_pc + 4, 1, 0);
|
}
|
}
|
else
|
else
|
PRINTF("%08x: : xxxxxxxx ITLB miss follows", pc);
|
PRINTF("%08lx: : xxxxxxxx ITLB miss follows", pc);
|
|
|
PRINTF(" (next insn) %s", (delay_insn?"(delay insn)":""));
|
PRINTF(" (next insn) %s", (delay_insn?"(delay insn)":""));
|
for(i = 0; i < MAX_GPRS; i++) {
|
for(i = 0; i < MAX_GPRS; i++) {
|
if (i % 4 == 0)
|
if (i % 4 == 0)
|
PRINTF("\n");
|
PRINTF("\n");
|
| Line 580... |
Line 585... |
setsprbits(SPR_VR, SPR_VR_VER, config.cpu.ver);
|
setsprbits(SPR_VR, SPR_VR_VER, config.cpu.ver);
|
setsprbits(SPR_VR, SPR_VR_REV, config.cpu.rev);
|
setsprbits(SPR_VR, SPR_VR_REV, config.cpu.rev);
|
mtspr(SPR_SR, config.cpu.sr);
|
mtspr(SPR_SR, config.cpu.sr);
|
|
|
pcnext = 0x0; /* MM1409: All programs should start at reset vector entry! */
|
pcnext = 0x0; /* MM1409: All programs should start at reset vector entry! */
|
if (config.sim.verbose) PRINTF ("Starting at 0x%08x\n", pcnext);
|
if (config.sim.verbose) PRINTF ("Starting at 0x%08lx\n", pcnext);
|
pc = pcnext;
|
pc = pcnext;
|
pc_phy = pc;
|
pc_phy = pc;
|
pcnext += 4;
|
pcnext += 4;
|
debug(1, "reset ...\n");
|
debug(1, "reset ...\n");
|
|
|
