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[/] [or1k/] [tags/] [nog_patch_39/] [or1ksim/] [cpu/] [or32/] [execute.c] - Diff between revs 1308 and 1319

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Rev 1308 Rev 1319
Line 434... Line 434...
      fprintf (runtime.sim.fexe_log, "--------------------- %8i instruction ---------------------\n", runtime.cpu.instructions);
      fprintf (runtime.sim.fexe_log, "--------------------- %8i instruction ---------------------\n", runtime.cpu.instructions);
    }
    }
    switch (config.sim.exe_log_type) {
    switch (config.sim.exe_log_type) {
    case EXE_LOG_HARDWARE:
    case EXE_LOG_HARDWARE:
      fprintf (runtime.sim.fexe_log, "\nEXECUTED(%11u): %.8lx:  ", runtime.cpu.instructions, i);
      fprintf (runtime.sim.fexe_log, "\nEXECUTED(%11u): %.8lx:  ", runtime.cpu.instructions, i);
      fprintf (runtime.sim.fexe_log, "%.2x%.2x", evalsim_mem8(i), evalsim_mem8(i + 1));
      fprintf (runtime.sim.fexe_log, "%.2x%.2x", evalsim_mem8_void(i), evalsim_mem8_void(i + 1));
      fprintf (runtime.sim.fexe_log, "%.2x%.2x", evalsim_mem8(i + 2), evalsim_mem8(i + 3));
      fprintf (runtime.sim.fexe_log, "%.2x%.2x", evalsim_mem8_void(i + 2), evalsim_mem8_void(i + 3));
      for(i = 0; i < MAX_GPRS; i++) {
      for(i = 0; i < MAX_GPRS; i++) {
        if (i % 4 == 0)
        if (i % 4 == 0)
          fprintf(runtime.sim.fexe_log, "\n");
          fprintf(runtime.sim.fexe_log, "\n");
        fprintf (runtime.sim.fexe_log, "GPR%2lu: %.8lx  ", i, reg[i]);
        fprintf (runtime.sim.fexe_log, "GPR%2lu: %.8lx  ", i, reg[i]);
      }
      }
Line 466... Line 466...
 
 
          for (i = 0; i < num_op; i++)
          for (i = 0; i < num_op; i++)
            if (op[i + MAX_OPERANDS] & OPTYPE_DIS) {
            if (op[i + MAX_OPERANDS] & OPTYPE_DIS) {
              j=1;
              j=1;
              fprintf (runtime.sim.fexe_log, "EA =%08lx PA =%08lx ", op[i],
              fprintf (runtime.sim.fexe_log, "EA =%08lx PA =%08lx ", op[i],
                       dmmu_translate(op[i],0));
                       peek_into_dtlb(op[i],0,0));
            } else if ((op[i + MAX_OPERANDS] & OPTYPE_REG) && op[i]) {
            } else if ((op[i + MAX_OPERANDS] & OPTYPE_REG) && op[i]) {
              fprintf (runtime.sim.fexe_log, "r%-2li=%08lx ", op[i],
              fprintf (runtime.sim.fexe_log, "r%-2li=%08lx ", op[i],
                       evalsim_reg32 (op[i]));
                       evalsim_reg32 (op[i]));
            } else
            } else
              fprintf (runtime.sim.fexe_log, "             ");
              fprintf (runtime.sim.fexe_log, "             ");
Line 502... Line 502...
  else {
  else {
    PRINTF("INTERNAL SIMULATOR ERROR:\n");
    PRINTF("INTERNAL SIMULATOR ERROR:\n");
    PRINTF("no translation for currently executed instruction\n");
    PRINTF("no translation for currently executed instruction\n");
  }
  }
 
 
  generate_time_pretty (temp, runtime.sim.cycles * config.sim.clkcycle_ps);
  // generate_time_pretty (temp, runtime.sim.cycles * config.sim.clkcycle_ps);
  PRINTF(" (executed) [time %s, #%i]\n", temp, runtime.cpu.instructions);
  PRINTF(" (executed) [cycle %lld, #%lld]\n", runtime.sim.cycles, runtime.cpu.instructions);
  if (config.cpu.superscalar)
  if (config.cpu.superscalar)
    PRINTF ("Superscalar CYCLES: %u", runtime.cpu.supercycles);
    PRINTF ("Superscalar CYCLES: %u", runtime.cpu.supercycles);
  if (config.cpu.hazards)
  if (config.cpu.hazards)
    PRINTF ("  HAZARDWAIT: %u\n", runtime.cpu.hazardwait);
    PRINTF ("  HAZARDWAIT: %u\n", runtime.cpu.hazardwait);
  else
  else

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