| Line 29... |
Line 29... |
#include "trace.h"
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#include "trace.h"
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#include "pic.h"
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#include "pic.h"
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#include "abstract.h"
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#include "abstract.h"
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#include "fields.h"
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#include "fields.h"
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#define dprintf(x) printf x
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/* The representation of the DMA controllers */
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/* The representation of the DMA controllers */
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static struct dma_controller dmas[NR_DMAS];
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static struct dma_controller dmas[NR_DMAS];
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static unsigned long dma_read32( unsigned long addr );
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static unsigned long dma_read32( unsigned long addr );
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static void dma_write32( unsigned long addr, unsigned long value );
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static void dma_write32( unsigned long addr, unsigned long value );
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| Line 320... |
Line 318... |
if ( !TEST_FLAG( channel->regs.csr, DMA_CH_CSR, CH_EN ) )
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if ( !TEST_FLAG( channel->regs.csr, DMA_CH_CSR, CH_EN ) )
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continue;
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continue;
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/* Do we need to abort? */
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/* Do we need to abort? */
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if ( TEST_FLAG( channel->regs.csr, DMA_CH_CSR, STOP ) ) {
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if ( TEST_FLAG( channel->regs.csr, DMA_CH_CSR, STOP ) ) {
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dprintf(( "DMA: STOP requested\n" ));
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debug( 3, "DMA: STOP requested\n" );
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CLEAR_FLAG( channel->regs.csr, DMA_CH_CSR, CH_EN );
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CLEAR_FLAG( channel->regs.csr, DMA_CH_CSR, CH_EN );
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CLEAR_FLAG( channel->regs.csr, DMA_CH_CSR, BUSY );
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CLEAR_FLAG( channel->regs.csr, DMA_CH_CSR, BUSY );
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SET_FLAG( channel->regs.csr, DMA_CH_CSR, ERR );
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SET_FLAG( channel->regs.csr, DMA_CH_CSR, ERR );
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if ( TEST_FLAG( channel->regs.csr, DMA_CH_CSR, INE_ERR ) &&
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if ( TEST_FLAG( channel->regs.csr, DMA_CH_CSR, INE_ERR ) &&
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| Line 343... |
Line 341... |
continue;
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continue;
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}
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}
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/* If this is the first cycle of the transfer, initialize our state */
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/* If this is the first cycle of the transfer, initialize our state */
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if ( !TEST_FLAG( channel->regs.csr, DMA_CH_CSR, BUSY ) ) {
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if ( !TEST_FLAG( channel->regs.csr, DMA_CH_CSR, BUSY ) ) {
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dprintf(( "Starting new transfer\n" ));
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debug( 4, "DMA: Starting new transfer\n" );
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CLEAR_FLAG( channel->regs.csr, DMA_CH_CSR, DONE );
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CLEAR_FLAG( channel->regs.csr, DMA_CH_CSR, DONE );
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CLEAR_FLAG( channel->regs.csr, DMA_CH_CSR, ERR );
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CLEAR_FLAG( channel->regs.csr, DMA_CH_CSR, ERR );
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SET_FLAG( channel->regs.csr, DMA_CH_CSR, BUSY );
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SET_FLAG( channel->regs.csr, DMA_CH_CSR, BUSY );
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| Line 360... |
Line 358... |
/* Set our internal status */
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/* Set our internal status */
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dma_init_transfer( channel );
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dma_init_transfer( channel );
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/* Might need to skip descriptor */
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/* Might need to skip descriptor */
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if ( CHANNEL_ND_I( channel ) ) {
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if ( CHANNEL_ND_I( channel ) ) {
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dprintf(( "DMA: dma_nd_i asserted before dma_req_i, skipping descriptor\n" ));
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debug( 3, "DMA: dma_nd_i asserted before dma_req_i, skipping descriptor\n" );
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dma_channel_terminate_transfer( channel, 0 );
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dma_channel_terminate_transfer( channel, 0 );
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continue;
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continue;
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}
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}
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}
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}
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| Line 379... |
Line 377... |
/* Have we finished a whole chunk? */
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/* Have we finished a whole chunk? */
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channel->dma_ack_o = (channel->words_transferred % channel->chunk_size == 0);
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channel->dma_ack_o = (channel->words_transferred % channel->chunk_size == 0);
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/* When done with a chunk, check for dma_nd_i */
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/* When done with a chunk, check for dma_nd_i */
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if ( CHANNEL_ND_I( channel ) ) {
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if ( CHANNEL_ND_I( channel ) ) {
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dprintf(( "DMA: dma_nd_i asserted\n" ));
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debug( 3, "DMA: dma_nd_i asserted\n" );
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dma_channel_terminate_transfer( channel, 0 );
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dma_channel_terminate_transfer( channel, 0 );
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continue;
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continue;
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}
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}
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/* Are we done? */
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/* Are we done? */
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| Line 432... |
Line 430... |
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/* Take care of transfer termination */
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/* Take care of transfer termination */
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void dma_channel_terminate_transfer( struct dma_channel *channel, int generate_interrupt )
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void dma_channel_terminate_transfer( struct dma_channel *channel, int generate_interrupt )
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{
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{
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dprintf(( "DMA: Terminating transfer\n" ));
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debug( 4, "DMA: Terminating transfer\n" );
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/* Might be working in a linked list */
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/* Might be working in a linked list */
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if ( channel->load_next_descriptor_when_done ) {
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if ( channel->load_next_descriptor_when_done ) {
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dma_load_descriptor( channel );
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dma_load_descriptor( channel );
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dma_init_transfer( channel );
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dma_init_transfer( channel );
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