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{

  /* Base address in memory */

  unsigned long baseaddr;

  /* Which Ethernet MAC is this? */

  unsigned eth_number;

  /* Which DMA controller is this MAC connected to */

  unsigned dma;

        unsigned tx_channel;

        unsigned rx_channel;

  /* RX and TX file names and handles */

  const char *rxfile, *txfile;

        int txfd;

        int rxfd;

        off_t loopback_offset;

        /* Current TX state */

        struct

        {

                unsigned long bd_index;

                unsigned long bd;

                unsigned working, waiting_for_ack, error;

                unsigned packet_length;

                unsigned minimum_length, maximum_length;

                unsigned crc;

                unsigned bytes_left, bytes_sent;

        } tx;

        /* Current RX state */

        struct

        {

                unsigned long bd_index;

                unsigned long bd;

                int fd;

                off_t *offset;

                unsigned working, error, waiting_for_ack;

                unsigned packet_length, bytes_read, bytes_left;

        } rx;

  /* Visible registers */

  struct

  {

    unsigned long moder;

    unsigned long int_source;

    unsigned long int_mask;

    unsigned long ipgt;

    unsigned long ipgr1;

    unsigned long ipgr2;

    unsigned long packetlen;

    unsigned long collconf;

    unsigned long rx_bd_adr;

    unsigned long controlmoder;

    unsigned long miimoder;

    unsigned long miicommand;

    unsigned long miiaddress;

    unsigned long miitx_data;

    unsigned long miirx_data;

    unsigned long miistatus;

    unsigned long mac_addr0;

    unsigned long mac_addr1;

                /* Buffer descriptors */

                unsigned long bd_ram[ETH_BD_SPACE / 4];

  } regs;

};