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Line 19... |
*/
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*/
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#ifndef __MC_SSRAM_H
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#ifndef __MC_SSRAM_H
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#define __MC_SSRAM_H
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#define __MC_SSRAM_H
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/* TEMPLATE SELECTION */
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/* change #undef to #define */
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#define _MC_TEST_TEMPLATE1
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#undef _MC_TEST_TEMPLATE2
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#undef _MC_TEST_TEMPLATE3
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/* ------------------------ */
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/* memory configuration that must reflect mcmem.cfg */
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/* memory configuration that must reflect mcmem.cfg */
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#define MC_SSRAM_CSMASK 0xFE /* 8 bit mask for 8 chip selects. 1 SDRAM at CS, 0 something else at CS */
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#define MC_SSRAM_CSMASK 0xFE /* 8 bit mask for 8 chip selects. 1 SSRAM at CS, 0 something else at CS */
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typedef struct MC_SSRAM_CS
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typedef struct MC_SSRAM_CS
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{
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{
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unsigned char M;
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unsigned char M;
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} MC_SSRAM_CS;
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} MC_SSRAM_CS;
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| Line 38... |
Line 45... |
{ 0x0A },
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{ 0x0A },
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{ 0x0C },
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{ 0x0C },
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{ 0x0E },
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{ 0x0E },
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{ 0x10 } };
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{ 0x10 } };
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#define MC_SSRAM_FLAGS 0x000002FFLU /* MC_TEST_ flags... see mc_common.h */
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#define MC_SSRAM_TEST0 0x00000001LU /* no parity, bank after column, write enable */
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#define MC_SSRAM_TEST1 0x00000002LU /* parity */
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#define MC_SSRAM_TEST2 0x00000004LU /* bank after row */
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#define MC_SSRAM_TEST3 0x00000008LU /* RO */
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#define MC_SSRAM_TEST4 0x00000010LU /* - NOT DEFINED - */
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#define MC_SSRAM_TEST5 0x00000020LU /* - NOT DEFINED - */
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#ifdef _MC_TEST_TEMPLATE1
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#define MC_SSRAM_FLAGS 0x000002B8LU /* MC_TEST_ flags... see mc_common.h */
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#define MC_SSRAM_TESTS 0x00000005LU
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#endif
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#define MC_SSRAM_TEST0 0x00000001LU
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#ifdef _MC_TEST_TEMPLATE2
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#define MC_SSRAM_TEST1 0x00000002LU
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#define MC_SSRAM_FLAGS 0x00000128LU /* MC_TEST_ flags... see mc_common.h */
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#define MC_SSRAM_TEST2 0x00000004LU
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#define MC_SSRAM_TESTS 0x00000008LU
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#define MC_SSRAM_TEST3 0x00000008LU
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#endif
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#define MC_SSRAM_TEST4 0x00000010LU
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#define MC_SSRAM_TEST5 0x00000020LU
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#ifdef _MC_TEST_TEMPLATE3
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#define MC_SSRAM_FLAGS 0x000007FFLU /* MC_TEST_ flags... see mc_common.h */
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#define MC_SSRAM_TESTS 0x0000003FLU
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#define MC_SSRAM_TESTS 0x0000003FLU
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#endif
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#endif
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No newline at end of file
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No newline at end of file
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#endif
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