OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [nog_patch_40/] [or1ksim/] [sim.cfg] - Diff between revs 897 and 1021

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 897 Rev 1021
Line 95... Line 95... 
 
 
 
 
     log = ""
 
     log = ""
 
        filename, where to log memory accesses to, no log, if log command is not specified
 
        filename, where to log memory accesses to, no log, if log command is not specified
 
*/
 
*/
 
 
 
 
 
 
 
 
 
section memory
 
section memory
 
  /*random_seed = 12345
 
  /*random_seed = 12345
 
  type = random*/
 
  type = random*/
 
  pattern = 0x00
 
  pattern = 0x00
 
  type = unknown /* Fastest */
 
  type = unknown /* Fastest */
 
 
 
 
 
  nmemories = 2
 
 
 
 
 
  nmemories = 3
 
  device 0
 
  device 0
 
    name = "FLASH"
 
    name = "FLASH"
 
    ce = 0
 
    ce = 0
 
    baseaddr = 0x00000000
 
    baseaddr = 0xf0000000
 
    size = 0x00200000
 
    size = 0x00800000
 
    delayr = 10
 
    delayr = 10
 
    delayw = -1
 
    delayw = -1
 
  enddevice
 
  enddevice
 
 
 
 
 
  device 1
 
  device 1
 
    name = "RAM"
 
    name = "RAM"
 
    ce = 1
 
    ce = 1
 
    baseaddr = 0x40000000
 
    baseaddr = 0x00000000
 
    size = 0x00200000
 
    size = 0x00400000
 
    delayr = 2
 
    delayr = 1
 
    delayw = 4
 
    delayw = 2
 
 
 
  enddevice
 
 
 
 
 
 
 
  device 2
 
 
 
    name = "SRAM"
 
 
 
    ce = 2
 
 
 
    baseaddr = 0x08000000
 
 
 
    size = 0x00400000
 
 
 
    delayr = 1
 
 
 
    delayw = 2
 
  enddevice
 
  enddevice
 
end
 
end
 
 
 
 
 
 
 
 
 
/* IMMU SECTION
 
/* IMMU SECTION
Line 154... Line 165... 
    missdelay = 
    missdelay = 
       number of cycles immu miss costs
 
       number of cycles immu miss costs
 
*/
 
*/
 
 
 
 
 
section immu
 
section immu
 
  enabled = 0
 
  enabled = 1
 
  nsets = 32
 
  nsets = 64
 
  nways = 1
 
  nways = 1
 
  pagesize = 8192
 
  pagesize = 8192
 
  hitdelay = 0
 
  hitdelay = 0
 
  missdelay = 0
 
  missdelay = 0
 
end
 
end
Line 195... Line 206... 
    missdelay = 
    missdelay = 
       number of cycles dmmu miss costs
 
       number of cycles dmmu miss costs
 
*/
 
*/
 
 
 
 
 
section dmmu
 
section dmmu
 
  enabled = 0
 
  enabled = 1
 
  nsets = 32
 
  nsets = 64
 
  nways = 1
 
  nways = 1
 
  pagesize = 8192
 
  pagesize = 8192
 
  hitdelay = 0
 
  hitdelay = 0
 
  missdelay = 0
 
  missdelay = 0
 
end
 
end
Line 233... Line 244... 
    missdelay = 
    missdelay = 
      number of cycles ic miss costs
 
      number of cycles ic miss costs
 
*/
 
*/
 
 
 
 
 
section ic
 
section ic
 
  enabled = 0
 
  enabled = 1
 
  nsets = 512
 
  nsets = 256
 
  nways = 1
 
  nways = 1
 
  blocksize = 16
 
  blocksize = 16
 
  hitdelay = 0
 
  hitdelay = 0
 
  missdelay = 0
 
  missdelay = 0
 
end
 
end
Line 277... Line 288... 
   store_missdelay = 
   store_missdelay = 
      number of cycles dc load miss costs
 
      number of cycles dc load miss costs
 
*/
 
*/
 
 
 
 
 
section dc
 
section dc
 
  enabled = 0
 
  enabled = 1
 
  nsets = 512
 
  nsets = 256
 
  nways = 1
 
  nways = 1
 
  blocksize = 16
 
  blocksize = 16
 
  load_hitdelay = 0
 
  load_hitdelay = 0
 
  load_missdelay = 0
 
  load_missdelay = 0
 
  store_hitdelay = 0
 
  store_hitdelay = 0
 
  store_missdelay = 0
 
  store_missdelay = 0
 
end
 
end
 
 
 
 
 
 
 
 
 
/* SIM SECTION
 
/* SIM SECTION
 
 
 
 
 
  This section specifies how or1ksim should behave.
 
  This section specifies how or1ksim should behave.
 
 
 
 
 
  verbose = 0/1
 
  verbose = 0/1
Line 364... Line 376... 
section sim
 
section sim
 
  /* verbose = 1 */
 
  /* verbose = 1 */
 
  debug = 0
 
  debug = 0
 
  profile = 0
 
  profile = 0
 
  prof_fn = "sim.profile"
 
  prof_fn = "sim.profile"
 
  mprofile = 0
 
 
 
  mprof_fn = "sim.mprofile"
 
 
 
 
 
 
 
  history = 1
 
  history = 1
 
  /* iprompt = 0 */
 
  /* iprompt = 0 */
 
  exe_log = 0
 
  exe_log = 0
 
  exe_log_type = hardware
 
  exe_log_type = software
 
  exe_log_start = 0
 
  exe_log_start = 0
 
  exe_log_end = 0
 
/*  exe_log_end = 20000000*/
 
  exe_log_marker = 0
 
  exe_log_marker = 10000
 
  exe_log_fn = "executed.log"
 
  exe_log_fn = "executed.log"
 
 
 
 
 
  spr_log = 0
 
  spr_log = 0
 
  spr_log_fn = "spr.log"
 
  spr_log_fn = "spr.log"
 
  clkcycle = 100ns
 
  clkcycle = 100ns
 
end
 
end
 
 
 
 
Line 454... Line 465... 
 
 
 
 
section cpu
 
section cpu
 
  ver = 0x1200
 
  ver = 0x1200
 
  rev = 0x0001
 
  rev = 0x0001
 
  /* upr = */
 
  /* upr = */
 
  sr = 0x00008003
 
 
 
  superscalar = 0
 
  superscalar = 0
 
  hazards = 0
 
  hazards = 0
 
  dependstats = 0
 
  dependstats = 0
 
  sbuf_len = 0
 
  sbuf_len = 0
 
end
 
end
Line 475... Line 485... 
 
 
 
 
section pm
 
section pm
 
  enabled = 0
 
  enabled = 0
 
end
 
end
 
 
 
 
 
 
 
 
 
/* BPB SECTION
 
/* BPB SECTION
 
 
 
 
 
   This section specifies how branch prediction should behave.
 
   This section specifies how branch prediction should behave.
 
 
 
 
 
   enabled = 0/1
 
   enabled = 0/1
Line 535... Line 546... 
   vapi_id = 
   vapi_id = 
      Used to create "fake" vapi log file containing the JTAG proxy messages.
 
      Used to create "fake" vapi log file containing the JTAG proxy messages.
 
*/
 
*/
 
 
 
 
 
section debug
 
section debug
 
  enabled = 1
 
  enabled = 0
 
  gdb_enabled = 0
 
  gdb_enabled = 0
 
  server_port = 9999
 
  server_port = 9999
 
  vapi_id = 0xFFFF
 
 
 
end
 
end
 
 
 
 
 
 
 
 
 
/* MC SECTION
 
/* MC SECTION
 
 
 
 
Line 558... Line 568... 
   POC = 
   POC = 
      Power On Configuration register
 
      Power On Configuration register
 
*/
 
*/
 
 
 
 
 
section mc
 
section mc
 
  enabled = 0
 
  enabled = 1
 
  baseaddr = 0x60000000
 
  baseaddr = 0x93000000
 
  POC = 0x00000008                 /* Power on configuration register */
 
  POC = 0x00000008                 /* Power on configuration register */
 
end
 
end
 
 
 
 
 
 
 
 
 
/* UART SECTION
 
/* UART SECTION
Line 602... Line 612... 
  nuarts = 1
 
  nuarts = 1
 
 
 
 
 
  device 0
 
  device 0
 
    baseaddr = 0x90000000
 
    baseaddr = 0x90000000
 
    irq = 2
 
    irq = 2
 
    rxfile = "/tmp/uart0.rx"
 
    rxfile = "uart0.rx"
 
    txfile = "/tmp/uart0.tx"
 
    txfile = "uart0.tx"
 
    jitter = -1                     /* async behaviour */
 
    jitter = -1                     /* async behaviour */
 
 
 
    16550 = 1
 
  enddevice
 
  enddevice
 
end
 
end
 
 
 
 
 
 
 
 
 
/* DMA SECTION
 
/* DMA SECTION
Line 630... Line 641... 
        VAPI id of this instance
 
        VAPI id of this instance
 
*/
 
*/
 
 
 
 
 
section dma
 
section dma
 
  ndmas = 0
 
  ndmas = 0
 
 
 
 
 
/*
 
/*
 
  device 0
 
  device 0
 
    baseaddr = 0x90000000
 
    baseaddr = 0x9a000000
 
    irq = 4
 
    irq = 11
 
  enddevice
 
  enddevice
 
*/
 
*/
 
end
 
end
 
 
 
 
 
 
 
 
Line 682... Line 694... 
*/
 
*/
 
 
 
 
 
section ethernet
 
section ethernet
 
  nethernets = 1
 
  nethernets = 1
 
 
 
 
 
 
 
 
 
  device 0
 
  device 0
 
    baseaddr = 0x88000000
 
    baseaddr = 0x92000000
 
    dma = 0
 
    dma = 0
 
    irq = 15
 
    irq = 4
 
    rtx_type = 0
 
    rtx_type = 1
 
    tx_channel = 0
 
    tx_channel = 0
 
    rx_channel = 1
 
    rx_channel = 1
 
    rxfile = "/tmp/eth0.rx"
 
    rxfile = "eth0.rx"
 
    txfile = "/tmp/eth0.tx"
 
    txfile = "eth0.tx"
 
    sockif = "lo"
 
    sockif = "eth0"
 
  enddevice
 
  enddevice
 
 
 
 
 
end
 
end
 
 
 
 
 
 
 
 
 
/* GPIO SECTION
 
/* GPIO SECTION
 
 
 
 
 
   This section configures the GPIOs
 
   This section configures the GPIOs
 
 
 
 
 
   ngpios = 
   ngpios =
Line 721... Line 732... 
 
 
 
 
section gpio
 
section gpio
 
  ngpios = 1
 
  ngpios = 1
 
 
 
 
 
  device 0
 
  device 0
 
    baseaddr = 0xA0000000
 
    baseaddr = 0x91000000
 
    irq = 23
 
    irq = 3
 
    base_vapi_id = 0x0200
 
    base_vapi_id = 0x0200
 
  enddevice
 
  enddevice
 
end
 
end
 
 
 
 
 
/* VGA SECTION
 
/* VGA SECTION
Line 752... Line 763... 
 
 
 
 
section vga
 
section vga
 
  nvgas = 1
 
  nvgas = 1
 
 
 
 
 
  device 0
 
  device 0
 
    baseaddr = 0xb0000000
 
    baseaddr = 0x97100000
 
    irq = 20
 
    irq = 8
 
    refresh_rate = 100000
 
    refresh_rate = 100000
 
    filename = "primary"
 
    filename = "primary"
 
  enddevice
 
  enddevice
 
end
 
end
 
 
 
 
 
 
 
 
 
 
 
/* TICK TIMER SECTION
 
 
 
 
 
 
 
    This section configures tick timer
 
 
 
 
 
 
 
    enabled = 0/1
 
 
 
      whether tick timer is enabled
 
 
 
 
 
 
 
    irq = 
 
 
      irq number
 
 
 
*/
 
 
 
/*
 
 
 
section tick
 
 
 
  enabled = 1
 
 
 
  irq = 0
 
 
 
end
 
 
 
*/
 
 
 
 
 
/* FB SECTION
 
/* FB SECTION
 
 
 
 
 
    This section configures the frame buffer
 
    This section configures the frame buffer
 
 
 
 
 
    enabled = 0/1
 
    enabled = 0/1
Line 781... Line 810... 
      template name for generated names (e.g. "primary" produces "primary0023.bmp")
 
      template name for generated names (e.g. "primary" produces "primary0023.bmp")
 
*/
 
*/
 
 
 
 
 
section fb
 
section fb
 
  enabled = 1
 
  enabled = 1
 
  baseaddr = 0xb8000000
 
  baseaddr = 0x97000000
 
  refresh_rate = 100000
 
  refresh_rate = 1000000
 
  filename = "primary"
 
  filename = "primary"
 
end
 
end
 
 
 
 
 
 
 
 
 
/* KBD SECTION
 
/* KBD SECTION
 
 
 
 
 
    This section configures the PS/2 compatible keyboard
 
    This section configures the PS/2 compatible keyboard
 
 
 
 
 
    enabled = 0/1
 
    enabled = 0/1
Line 802... Line 832... 
      filename, where to read data from
 
      filename, where to read data from
 
*/
 
*/
 
 
 
 
 
section kbd
 
section kbd
 
  enabled = 1
 
  enabled = 1
 
  irq = 21
 
  irq = 5
 
  baseaddr = 0xb1000000
 
  baseaddr = 0x94000000
 
  rxfile = "/tmp/kbd.rx"
 
  rxfile = "kbd.rx"
 
end
 
end
 
 
 
 
 
 
 
 
 
/* ATA SECTION
 
/* ATA SECTION
 
 
 
 
Line 856... Line 886... 
 
 
 
 
section ata
 
section ata
 
  natas = 1
 
  natas = 1
 
 
 
 
 
  device 0
 
  device 0
 
    baseaddr = 0xc8000000
 
    baseaddr = 0x9e000000
 
    irq = 21
 
    irq = 15
 
 
 
 
 
    dev_type0   = 1
 
    dev_type0   = 1
 
    dev_file0   = "/tmp/sim_atadev0"
 
    dev_file0   = "/tmp/sim_atadev0"
 
    dev_size0   = 1
 
    dev_size0   = 1
 
    dev_packet0 = 0
 
    dev_packet0 = 0

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.