| Line 59... |
Line 59... |
unsigned long cur_vadd;
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unsigned long cur_vadd;
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/* Temporary variable, which specifies how many cycles did the memory acces require */
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/* Temporary variable, which specifies how many cycles did the memory acces require */
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extern int mem_cycles;
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extern int mem_cycles;
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/* It returns physical address. */
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inline unsigned long translate_vrt_to_phy_add(unsigned long virtaddr, int write_access)
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{
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if (config.ic.tagtype == CT_NONE)
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return immu_translate(virtaddr, write_access);
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else
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if (config.ic.tagtype == CT_VIRTUAL) {
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return immu_translate(virtaddr, write_access);
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}
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else if (config.dc.tagtype == CT_PHYSICAL) {
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unsigned long phyaddr = immu_translate(virtaddr, write_access);
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return phyaddr;
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}
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else {
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printf("INTERNAL ERROR: Unknown insn cache type.\n");
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cont_run = 0;
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}
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return -1;
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}
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/* Calls IMMU translation routines before simulating insn
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cache for virtually indexed insn cache or after simulating insn cache
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for physically indexed insn cache. It returns physical address. */
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static inline unsigned long simulate_ic_mmu_fetch(unsigned long virtaddr)
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{
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unsigned long phyaddr;
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if ((phyaddr = translate_vrt_to_phy_add(virtaddr, 0)) != -1) {
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ic_simulate_fetch(phyaddr);
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return phyaddr;
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}
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else {
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printf("INTERNAL ERROR: Unknown insn cache type.\n");
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cont_run = 0;
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}
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return -1;
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}
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/* Calls DMMU translation routines (load cycles) before simulating data
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cache for virtually indexed data cache or after simulating data cache
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for physically indexed data cache. It returns physical address. */
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static inline unsigned long simulate_dc_mmu_load(unsigned long virtaddr)
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{
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if (config.dc.tagtype == CT_NONE)
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return dmmu_translate(virtaddr, 0);
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else
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if (config.dc.tagtype == CT_VIRTUAL) {
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dc_simulate_read(virtaddr);
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return dmmu_translate(virtaddr, 0);
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}
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else if (config.dc.tagtype == CT_PHYSICAL) {
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unsigned long phyaddr = dmmu_translate(virtaddr, 0);
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dc_simulate_read(phyaddr);
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return phyaddr;
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}
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else {
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printf("INTERNAL ERROR: Unknown data cache type.\n");
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cont_run = 0;
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}
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return -1;
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}
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/* Calls DMMU translation routines (store cycles) before simulating data
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cache for virtually indexed data cache or after simulating data cache
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for physically indexed data cache. It returns physical address. */
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static inline unsigned long simulate_dc_mmu_store(unsigned long virtaddr)
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{
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if (config.dc.tagtype == CT_NONE)
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return dmmu_translate(virtaddr, 0);
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else
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if (config.dc.tagtype == CT_VIRTUAL) {
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dc_simulate_write(virtaddr);
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return dmmu_translate(virtaddr, 1);
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}
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else if (config.dc.tagtype == CT_PHYSICAL) {
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unsigned long phyaddr = dmmu_translate(virtaddr, 1);
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dc_simulate_write(phyaddr);
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return phyaddr;
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}
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else {
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printf("INTERNAL ERROR: Unknown data cache type.\n");
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cont_run = 0;
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}
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return -1;
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}
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/* Calculates bit mask to fit the data */
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/* Calculates bit mask to fit the data */
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unsigned long bit_mask (unsigned long data) {
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unsigned long bit_mask (unsigned long data) {
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int i = 0;
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int i = 0;
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data--;
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data--;
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while (data >> i)
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while (data >> i)
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| Line 363... |
Line 270... |
if (memaddr & 3) {
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if (memaddr & 3) {
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except_handle (EXCEPT_ALIGN, memaddr);
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except_handle (EXCEPT_ALIGN, memaddr);
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return 0;
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return 0;
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}
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}
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if (config.debug.enabled)
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*breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */
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cur_vadd = memaddr;
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cur_vadd = memaddr;
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memaddr = simulate_dc_mmu_load(memaddr);
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memaddr = dmmu_translate(memaddr, 0);
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if (pending.valid)
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if (pending.valid)
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return 0;
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return 0;
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if (config.debug.enabled)
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temp = dc_simulate_read(memaddr, 4);
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*breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */
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temp = evalsim_mem32(memaddr);
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if (!cur_area) {
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if (!cur_area) {
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printf("EXCEPTION: read out of memory (32-bit access to %.8lx)\n", memaddr);
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printf("EXCEPTION: read out of memory (32-bit access to %.8lx)\n", memaddr);
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except_handle(EXCEPT_BUSERR, cur_vadd);
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except_handle(EXCEPT_BUSERR, cur_vadd);
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temp = 0;
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temp = 0;
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}
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}
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| Line 394... |
Line 303... |
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if (config.sim.mprofile)
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if (config.sim.mprofile)
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mprofile (memaddr, MPROF_32 | MPROF_FETCH);
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mprofile (memaddr, MPROF_32 | MPROF_FETCH);
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// memaddr = simulate_ic_mmu_fetch(memaddr);
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// memaddr = simulate_ic_mmu_fetch(memaddr);
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cur_vadd = pc;
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cur_vadd = pc;
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IFF (config.ic.enabled) ic_simulate_fetch(memaddr);
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if (config.debug.enabled)
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if (config.debug.enabled)
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*breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */
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*breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */
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if (config.ic.enabled)
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temp = ic_simulate_fetch(memaddr);
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else
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temp = evalsim_mem32(memaddr);
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temp = evalsim_mem32(memaddr);
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if (!cur_area) {
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if (!cur_area) {
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printf("EXCEPTION: read out of memory (32-bit access to %.8lx)\n", memaddr);
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printf("EXCEPTION: read out of memory (32-bit access to %.8lx)\n", memaddr);
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except_handle(EXCEPT_BUSERR, cur_vadd);
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except_handle(EXCEPT_BUSERR, cur_vadd);
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temp = 0;
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temp = 0;
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| Line 425... |
Line 336... |
if (memaddr & 1) {
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if (memaddr & 1) {
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except_handle (EXCEPT_ALIGN, memaddr);
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except_handle (EXCEPT_ALIGN, memaddr);
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return 0;
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return 0;
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}
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}
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if (config.debug.enabled)
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*breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */
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cur_vadd = memaddr;
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cur_vadd = memaddr;
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memaddr = simulate_dc_mmu_load(memaddr);
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memaddr = dmmu_translate(memaddr, 0);
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if (pending.valid)
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if (pending.valid)
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return 0;
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return 0;
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if (config.debug.enabled)
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temp = (unsigned short)dc_simulate_read(memaddr, 2);
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*breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */
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temp = evalsim_mem16(memaddr);
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if (!cur_area) {
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if (!cur_area) {
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printf("EXCEPTION: read out of memory (16-bit access to %.8lx)\n", memaddr);
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printf("EXCEPTION: read out of memory (16-bit access to %.8lx)\n", memaddr);
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except_handle(EXCEPT_BUSERR, cur_vadd);
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except_handle(EXCEPT_BUSERR, cur_vadd);
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temp = 0;
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temp = 0;
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}
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}
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| Line 451... |
Line 363... |
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/* Returns 8-bit values from mem array. */
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/* Returns 8-bit values from mem array. */
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unsigned char eval_mem8(unsigned long memaddr,int* breakpoint)
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unsigned char eval_mem8(unsigned long memaddr,int* breakpoint)
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{
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{
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unsigned long temp;
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unsigned char temp;
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if (config.sim.mprofile)
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if (config.sim.mprofile)
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mprofile (memaddr, MPROF_8 | MPROF_READ);
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mprofile (memaddr, MPROF_8 | MPROF_READ);
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if (config.debug.enabled)
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*breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */
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cur_vadd = memaddr;
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cur_vadd = memaddr;
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memaddr = simulate_dc_mmu_load(memaddr);
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memaddr = dmmu_translate(memaddr, 0);
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if (pending.valid)
|
if (pending.valid)
|
return 0;
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return 0;
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if (config.debug.enabled)
|
temp = (unsigned char)dc_simulate_read(memaddr, 1);
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*breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */
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temp = evalsim_mem8(memaddr);
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if (!cur_area) {
|
if (!cur_area) {
|
printf("EXCEPTION: read out of memory (8-bit access to %.8lx)\n", memaddr);
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printf("EXCEPTION: read out of memory (8-bit access to %.8lx)\n", memaddr);
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except_handle(EXCEPT_BUSERR, cur_vadd);
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except_handle(EXCEPT_BUSERR, cur_vadd);
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temp = 0;
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temp = 0;
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}
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}
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| Line 575... |
Line 488... |
except_handle (EXCEPT_ALIGN, memaddr);
|
except_handle (EXCEPT_ALIGN, memaddr);
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return;
|
return;
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}
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}
|
|
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cur_vadd = memaddr;
|
cur_vadd = memaddr;
|
memaddr = simulate_dc_mmu_store(memaddr);
|
memaddr = dmmu_translate(memaddr, 1);;
|
/* If we produced exception don't set anything */
|
/* If we produced exception don't set anything */
|
if (pending.valid)
|
if (pending.valid)
|
return;
|
return;
|
|
|
if (config.debug.enabled) {
|
if (config.debug.enabled) {
|
| Line 588... |
Line 501... |
}
|
}
|
|
|
if (cur_area->log)
|
if (cur_area->log)
|
fprintf (cur_area->log, "[%08x] -> write %08x\n", memaddr, value);
|
fprintf (cur_area->log, "[%08x] -> write %08x\n", memaddr, value);
|
|
|
setsim_mem32(memaddr, value);
|
dc_simulate_write(memaddr, value, 4);
|
}
|
}
|
|
|
/* Set mem, 16-bit. Big endian version. */
|
/* Set mem, 16-bit. Big endian version. */
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|
|
void set_mem16(unsigned long memaddr, unsigned short value,int* breakpoint)
|
void set_mem16(unsigned long memaddr, unsigned short value,int* breakpoint)
|
| Line 604... |
Line 517... |
except_handle (EXCEPT_ALIGN, memaddr);
|
except_handle (EXCEPT_ALIGN, memaddr);
|
return;
|
return;
|
}
|
}
|
|
|
cur_vadd = memaddr;
|
cur_vadd = memaddr;
|
memaddr = simulate_dc_mmu_store(memaddr);
|
memaddr = dmmu_translate(memaddr, 1);;
|
/* If we produced exception don't set anything */
|
/* If we produced exception don't set anything */
|
if (pending.valid)
|
if (pending.valid)
|
return;
|
return;
|
|
|
if (config.debug.enabled) {
|
if (config.debug.enabled) {
|
| Line 617... |
Line 530... |
}
|
}
|
|
|
if (cur_area->log)
|
if (cur_area->log)
|
fprintf (cur_area->log, "[%08x] -> write %08x\n", memaddr, value);
|
fprintf (cur_area->log, "[%08x] -> write %08x\n", memaddr, value);
|
|
|
setsim_mem16(memaddr, value);
|
dc_simulate_write(memaddr, (unsigned long)value, 2);
|
}
|
}
|
|
|
/* Set mem, 8-bit. */
|
/* Set mem, 8-bit. */
|
|
|
void set_mem8(unsigned long memaddr, unsigned char value,int* breakpoint)
|
void set_mem8(unsigned long memaddr, unsigned char value,int* breakpoint)
|
{
|
{
|
if (config.sim.mprofile)
|
if (config.sim.mprofile)
|
mprofile (memaddr, MPROF_8 | MPROF_WRITE);
|
mprofile (memaddr, MPROF_8 | MPROF_WRITE);
|
|
|
cur_vadd = memaddr;
|
cur_vadd = memaddr;
|
memaddr = simulate_dc_mmu_store(memaddr);
|
memaddr = dmmu_translate(memaddr, 1);;
|
/* If we produced exception don't set anything */
|
/* If we produced exception don't set anything */
|
if (pending.valid) return;
|
if (pending.valid) return;
|
|
|
if (config.debug.enabled) {
|
if (config.debug.enabled) {
|
*breakpoint += CheckDebugUnit(DebugStoreAddress,memaddr); /* 28/05/01 CZ */
|
*breakpoint += CheckDebugUnit(DebugStoreAddress,memaddr); /* 28/05/01 CZ */
|
| Line 640... |
Line 553... |
}
|
}
|
|
|
if (cur_area->log)
|
if (cur_area->log)
|
fprintf (cur_area->log, "[%08x] -> write %08x\n", memaddr, value);
|
fprintf (cur_area->log, "[%08x] -> write %08x\n", memaddr, value);
|
|
|
setsim_mem8(memaddr, value);
|
dc_simulate_write(memaddr, (unsigned long)value, 1);
|
}
|
}
|
|
|
void dumpmemory(unsigned int from, unsigned int to, int disasm, int nl)
|
void dumpmemory(unsigned int from, unsigned int to, int disasm, int nl)
|
{
|
{
|
unsigned int i, j;
|
unsigned int i, j;
|
