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[/] [or1k/] [tags/] [nog_patch_42/] [or1ksim/] [cuc/] [verilog.c] - Diff between revs 925 and 926

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Rev 925 Rev 926
Line 132... Line 132...
    if (II_IS_LOAD (ii->index)) {
    if (II_IS_LOAD (ii->index)) {
      int nm;
      int nm;
      for (nm = 0; nm < f->nmsched; nm++) if (f->msched[nm] == REF (b, i)) break;
      for (nm = 0; nm < f->nmsched; nm++) if (f->msched[nm] == REF (b, i)) break;
      assert (nm < f->nmsched);
      assert (nm < f->nmsched);
 
 
      GEN ("  if (rst) t%x_%x <= #Tp 32'h0;\n", b, i);
      GEN ("  if (l_end[%i]) t%x_%x <= #Tp ", nls, b, i);
      GEN ("  else if (l_end[%i]) t%x_%x <= #Tp ", nls, b, i);
 
      switch (f->mtype[nm] & (MT_WIDTH | MT_SIGNED)) {
      switch (f->mtype[nm] & (MT_WIDTH | MT_SIGNED)) {
        case 1: GEN ("lwb_dat_i & 32'hff;\n");
        case 1: GEN ("lwb_dat_i & 32'hff;\n");
                break;
                break;
        case 2: GEN ("lwb_dat_i & 32'hffff;\n");
        case 2: GEN ("lwb_dat_i & 32'hffff;\n");
                break;
                break;
Line 156... Line 155...
  } else if (ii->index == II_LRBB) {
  } else if (ii->index == II_LRBB) {
    GEN ("  if (rst) t%x_%x <= #Tp 1'b0;\n", b, i);
    GEN ("  if (rst) t%x_%x <= #Tp 1'b0;\n", b, i);
    assert (f->bb[b].prev[0] >= 0 && f->bb[b].prev[0] != BBID_END);
    assert (f->bb[b].prev[0] >= 0 && f->bb[b].prev[0] != BBID_END);
    GEN ("  else if (bb_start[%i]) t%x_%x <= #Tp bb_stb[%i];\n", b, b, i, f->bb[b].prev[0]);
    GEN ("  else if (bb_start[%i]) t%x_%x <= #Tp bb_stb[%i];\n", b, b, i, f->bb[b].prev[0]);
  } else if (ii->index == II_REG) {
  } else if (ii->index == II_REG) {
    GEN ("  if (rst) t%x_%x <= #Tp 32'h0;\n", b, i);
 
    assert (ii->opt[1] == OPT_REF);
    assert (ii->opt[1] == OPT_REF);
    GEN ("  else if (");
    GEN ("  if (");
    if (f->bb[b].mdep) print_deps (fo, f, b, f->bb[b].mdep, 0);
    if (f->bb[b].mdep) print_deps (fo, f, b, f->bb[b].mdep, 0);
    else GEN ("bb_stb[%i]", b);
    else GEN ("bb_stb[%i]", b);
    GEN (") t%x_%x <= #Tp t%x_%x;\n",  b, i,
    GEN (") t%x_%x <= #Tp t%x_%x;\n",  b, i,
                    REF_BB (ii->op[1]), REF_I (ii->op[1]));
                    REF_BB (ii->op[1]), REF_I (ii->op[1]));
  }
  }

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