URL https://opencores.org/ocsvn/or1k/or1k/trunk

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[/] [or1k/] [tags/] [nog_patch_42/] [or1ksim/] [sim.cfg] - Diff between revs 599 and 624

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Rev 599	Rev 624
Line 108...	Line 108...
`nmemories = 2`	`nmemories = 2`
`device 0`	`device 0`
`name = "FLASH"`	`name = "FLASH"`
`ce = 0`	`ce = 0`
`baseaddr = 0x00000000`	`baseaddr = 0x00000000`
`size = 0x00100000`	`size = 0x000200000`
`delayr = 10`	`delayr = 10`
`delayw = -1`	`delayw = -1`
`enddevice`	`enddevice`

`device 1`	`device 1`
`name = "RAM"`	`name = "RAM"`
`ce = 1`	`ce = 1`
`baseaddr = 0x40000000`	`baseaddr = 0x04000000`
`size = 0x00100000`	`size = 0x04000000`
`delayr = 2`	`delayr = 2`
`delayw = 4`	`delayw = 4`
`enddevice`	`enddevice`
`end`	`end`

Line 326...	Line 326...

`exe_log_fn = ""`	`exe_log_fn = ""`
`where to put execution log in, used only if 'exe_log'`	`where to put execution log in, used only if 'exe_log'`
`is set`	`is set`

	`spr_log = 0/1`
	`whether log of writes/reads to/from sprs should be generated`

	`spr_log_fn = ""`
	`where to put sprs write/read log in, used onli if 'spr_log'`
	`is set`

`clkcycle = [ps\|ns\|us\|ms]`	`clkcycle = [ps\|ns\|us\|ms]`
`specifies time measurement for one cycle`	`specifies time measurement for one cycle`
`*/`	`*/`

`section sim`	`section sim`
Line 342...	Line 349...

`history = 1`	`history = 1`
`/* iprompt = 0 */`	`/* iprompt = 0 */`
`exe_log = 0`	`exe_log = 0`
`exe_log_fn = "executed.log"`	`exe_log_fn = "executed.log"`
`clkcycle = 4ns`	`spr_log = 1`
	`spr_log_fn = "spr.log"`
	`clkcycle = 100ns`
`end`	`end`


`/* SECTION VAPI`	`/* SECTION VAPI`

Line 502...	Line 511...
`POC =`	`POC =`
`Power On Configuration register`	`Power On Configuration register`
`*/`	`*/`

`section mc`	`section mc`
`enabled = 0`	`enabled = 1`
`baseaddr = 0xa0000000`	`baseaddr = 0x60000000`
`POC = 0x00000008 /* Power on configuration register */`	`POC = 0x00000008 /* Power on configuration register */`
`end`	`end`


`/* UART SECTION`	`/* UART SECTION`
Line 543...	Line 552...

`section uart`	`section uart`
`nuarts = 1`	`nuarts = 1`

`device 0`	`device 0`
`baseaddr = 0x80000000`	`baseaddr = 0x90000000`
`irq = 2`	`irq = 2`
`rxfile = "/tmp/uart0.rx"`	`rxfile = "/tmp/uart0.rx"`
`txfile = "/tmp/uart0.tx"`	`txfile = "/tmp/uart0.tx"`
`jitter = -1 /* async behaviour */`	`jitter = -1 /* async behaviour */`
`enddevice`	`enddevice`
Line 572...	Line 581...
`vapi_id =`	`vapi_id =`
`VAPI id of this instance`	`VAPI id of this instance`
`*/`	`*/`

`section dma`	`section dma`
`ndmas = 1`	`ndmas = 0`
	`/*`
`device 0`	`device 0`
`baseaddr = 0x90000000`	`baseaddr = 0x90000000`
`irq = 4`	`irq = 4`
`enddevice`	`enddevice`
	`*/`
`end`	`end`


`/* ETHERNET SECTION`	`/* ETHERNET SECTION`

Line 613...	Line 623...
`vapi_id =`	`vapi_id =`
`VAPI id of this instance`	`VAPI id of this instance`
`*/`	`*/`

`section ethernet`	`section ethernet`
`nethernets = 1`	`nethernets = 0`

	`/*`
`device 0`	`device 0`
`baseaddr = 0x88000000`	`baseaddr = 0x88000000`
`dma = 0`	`dma = 0`
`tx_channel = 0`	`tx_channel = 0`
`rx_channel = 1`	`rx_channel = 1`
`rxfile = "/tmp/eth0.rx"`	`rxfile = "/tmp/eth0.rx"`
`txfile = "/tmp/eth0.tx"`	`txfile = "/tmp/eth0.tx"`
`enddevice`	`enddevice`
	`*/`
`end`	`end`

`/* GPIO SECTION`	`/* GPIO SECTION`

`This section configures GPIOs`	`This section configures GPIOs`
Line 649...	Line 661...

`section gpio`	`section gpio`
`ngpios = 1`	`ngpios = 1`

`device 0`	`device 0`
`baseaddr = 0xB0000000`	`baseaddr = 0xA0000000`
`irq = 23`	`irq = 23`
`base_vapi_id = 0x0200`	`base_vapi_id = 0x0200`
`enddevice`	`enddevice`
`end`	`end`

Line 661...	Line 673...

`This section configures tick timer`	`This section configures tick timer`

`enabled = 0/1`	`enabled = 0/1`
`whether tick timer is enabled`	`whether tick timer is enabled`

	`irq =`
	`irq number`
`*/`	`*/`

`section tick`	`section tick`
`enabled = 0`	`enabled = 0`
	`irq = 3`
`end`	`end`

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[/] [or1k/] [tags/] [nog_patch_42/] [or1ksim/] [sim.cfg] - Diff between revs 599 and 624