Line 64... |
Line 64... |
*/
|
*/
|
void eth_controller_tx_clock( struct eth_device *eth )
|
void eth_controller_tx_clock( struct eth_device *eth )
|
{
|
{
|
int breakpoint = 0;
|
int breakpoint = 0;
|
int bAdvance = 1;
|
int bAdvance = 1;
|
|
#ifdef HAVE_ETH_PHY
|
struct sockaddr_ll sll;
|
struct sockaddr_ll sll;
|
|
#endif /* HAVE_ETH_PHY */
|
long nwritten;
|
long nwritten;
|
unsigned long read_word;
|
unsigned long read_word;
|
|
|
switch (eth->tx.state) {
|
switch (eth->tx.state) {
|
case ETH_TXSTATE_IDLE:
|
case ETH_TXSTATE_IDLE:
|
Line 172... |
Line 173... |
/* send packet */
|
/* send packet */
|
switch (eth->rtx_type) {
|
switch (eth->rtx_type) {
|
case ETH_RTX_FILE:
|
case ETH_RTX_FILE:
|
nwritten = write( eth->txfd, eth->tx_buff, eth->tx.packet_length );
|
nwritten = write( eth->txfd, eth->tx_buff, eth->tx.packet_length );
|
break;
|
break;
|
|
#ifdef HAVE_ETH_PHY
|
case ETH_RTX_SOCK:
|
case ETH_RTX_SOCK:
|
memset(&sll, 0, sizeof(sll));
|
memset(&sll, 0, sizeof(sll));
|
sll.sll_ifindex = eth->ifr.ifr_ifindex;
|
sll.sll_ifindex = eth->ifr.ifr_ifindex;
|
nwritten = sendto(eth->rtx_sock, eth->tx_buff, eth->tx.packet_length, 0, (struct sockaddr *)&sll, sizeof(sll));
|
nwritten = sendto(eth->rtx_sock, eth->tx_buff, eth->tx.packet_length, 0, (struct sockaddr *)&sll, sizeof(sll));
|
break;
|
#endif /* HAVE_ETH_PHY */
|
}
|
}
|
|
|
/* set BD status */
|
/* set BD status */
|
if (nwritten == eth->tx.packet_length) {
|
if (nwritten == eth->tx.packet_length) {
|
CLEAR_FLAG (eth->tx.bd, ETH_TX_BD, READY);
|
CLEAR_FLAG (eth->tx.bd, ETH_TX_BD, READY);
|
Line 488... |
Line 490... |
memset( eths, 0, sizeof(eths) );
|
memset( eths, 0, sizeof(eths) );
|
|
|
for ( i = 0; i < MAX_ETHERNETS; ++ i ) {
|
for ( i = 0; i < MAX_ETHERNETS; ++ i ) {
|
struct eth_device *eth = &(eths[i]);
|
struct eth_device *eth = &(eths[i]);
|
|
|
|
if (!HAVE_ETH_PHY && eth->rtx_type == ETH_RTX_SOCK) {
|
|
fprintf (stderr, "Ethernet phy not enabled in this configuration. Configure with --enable-ethphy.\n");
|
|
exit (1);
|
|
}
|
eth->eth_number = i;
|
eth->eth_number = i;
|
eth_reset_controller( eth );
|
eth_reset_controller( eth );
|
if ( eth->baseaddr && first_time )
|
if ( eth->baseaddr && first_time )
|
register_memoryarea( eth->baseaddr, ETH_ADDR_SPACE, 4, eth_read32, eth_write32 );
|
register_memoryarea( eth->baseaddr, ETH_ADDR_SPACE, 4, eth_read32, eth_write32 );
|
}
|
}
|
Line 505... |
Line 511... |
|
|
static void eth_reset_controller(struct eth_device *eth)
|
static void eth_reset_controller(struct eth_device *eth)
|
{
|
{
|
int i = eth->eth_number;
|
int i = eth->eth_number;
|
int j;
|
int j;
|
|
#ifdef HAVE_ETH_PHY
|
struct sockaddr_ll sll;
|
struct sockaddr_ll sll;
|
|
#endif /* HAVE_ETH_PHY */
|
|
|
eth->baseaddr = config.ethernets[i].baseaddr;
|
eth->baseaddr = config.ethernets[i].baseaddr;
|
|
|
if ( eth->baseaddr != 0 ) {
|
if ( eth->baseaddr != 0 ) {
|
/* Mark which DMA controller and channels */
|
/* Mark which DMA controller and channels */
|
Line 538... |
Line 546... |
S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH )) < 0 )
|
S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH )) < 0 )
|
fprintf( stderr, "Cannot open Ethernet TX file \"%s\"\n", eth->txfile );
|
fprintf( stderr, "Cannot open Ethernet TX file \"%s\"\n", eth->txfile );
|
eth->loopback_offset = lseek( eth->txfd, 0, SEEK_END );
|
eth->loopback_offset = lseek( eth->txfd, 0, SEEK_END );
|
|
|
break;
|
break;
|
|
#ifdef HAVE_ETH_PHY
|
case ETH_RTX_SOCK:
|
case ETH_RTX_SOCK:
|
/* (Re-)open TX/RX sockets */
|
/* (Re-)open TX/RX sockets */
|
if (eth->rtx_sock != 0)
|
if (eth->rtx_sock != 0)
|
break;
|
break;
|
|
|
Line 588... |
Line 597... |
recv(eth->rtx_sock, eth->rx_buff, j, 0);
|
recv(eth->rtx_sock, eth->rx_buff, j, 0);
|
} while (j);
|
} while (j);
|
debug (3, "\n");
|
debug (3, "\n");
|
|
|
break;
|
break;
|
|
#endif /* HAVE_ETH_PHY */
|
}
|
}
|
|
|
/* Set registers to default values */
|
/* Set registers to default values */
|
memset( &(eth->regs), 0, sizeof(eth->regs) );
|
memset( &(eth->regs), 0, sizeof(eth->regs) );
|
eth->regs.moder = 0x0000A000;
|
eth->regs.moder = 0x0000A000;
|