| Line 16... |
Line 16... |
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/* What is the last address in ram that is used by this program */
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/* What is the last address in ram that is used by this program */
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#define TEXT_END_ADD (FLASH_START + (FLASH_SIZE / 2))
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#define TEXT_END_ADD (FLASH_START + (FLASH_SIZE / 2))
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#define DATA_END_ADD (RAM_START + (RAM_SIZE / 2))
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#define DATA_END_ADD (RAM_START + (RAM_SIZE / 2))
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#define TLB_TEXT_SET_NB 6
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#define TLB_TEXT_SET_NB 8
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#define TLB_DATA_SET_NB 2
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#define TLB_DATA_SET_NB 4
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/* MMU page size */
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/* MMU page size */
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#define PAGE_SIZE 8192
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#define PAGE_SIZE 8192
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/* Number of DTLB sets used (power of 2, max is 256) */
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/* Number of DTLB sets used (power of 2, max is 256) */
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#define DTLB_SETS 32
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#define DTLB_SETS 64
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/* Number of DTLB ways (1, 2, 3 etc., max is 4). */
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/* Number of DTLB ways (1, 2, 3 etc., max is 4). */
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#define DTLB_WAYS 1
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#define DTLB_WAYS 1
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/* Number of ITLB sets used (power of 2, max is 256) */
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/* Number of ITLB sets used (power of 2, max is 256) */
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#define ITLB_SETS 32
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#define ITLB_SETS 64
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/* Number of ITLB ways (1, 2, 3 etc., max is 4). */
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/* Number of ITLB ways (1, 2, 3 etc., max is 4). */
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#define ITLB_WAYS 1
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#define ITLB_WAYS 1
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/* TLB mode codes */
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/* TLB mode codes */
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| Line 66... |
Line 66... |
#define TEST_JUMP(x) copy_jump (((x) & (RAM_SIZE/2 - 1)) + DATA_END_ADD); call (x)
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#define TEST_JUMP(x) copy_jump (((x) & (RAM_SIZE/2 - 1)) + DATA_END_ADD); call (x)
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/* Extern functions */
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/* Extern functions */
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extern void lo_dmmu_en (void);
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extern void lo_dmmu_en (void);
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extern void lo_immu_en (void);
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extern void lo_immu_en (void);
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extern int lo_dtlb_ci_test (unsigned long, unsigned long);
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extern int lo_itlb_ci_test(unsigned long, unsigned long);
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extern void testjump(unsigned long phy_addr, unsigned long virt_addr);
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extern void testjump(unsigned long phy_addr, unsigned long virt_addr);
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extern void (*jr)(void);
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extern void (*jr)(void);
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/* Local functions prototypes */
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/* Local functions prototypes */
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void dmmu_disable (void);
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void dmmu_disable (void);
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| Line 787... |
Line 789... |
dmmu_disable();
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dmmu_disable();
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return 0;
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return 0;
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}
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}
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/* Data cache inhibit bit test
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Set and clear CI bit and check the pattern. */
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int dtlb_ci_test (void)
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{
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int i, j;
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unsigned long ea, ta, ret;
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/* Disable DMMU */
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dmmu_disable();
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/* Invalidate all entries in DTLB */
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for (i = 0; i < DTLB_WAYS; i++) {
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for (j = 0; j < DTLB_SETS; j++) {
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mtspr (SPR_DTLBMR_BASE(i) + j, 0);
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mtspr (SPR_DTLBTR_BASE(i) + j, 0);
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}
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}
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/* Set one to one translation for the use of this program */
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for (i = 0; i < TLB_DATA_SET_NB; i++) {
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ea = RAM_START + (i*PAGE_SIZE);
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ta = RAM_START + (i*PAGE_SIZE);
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mtspr (SPR_DTLBMR_BASE(0) + i, ea | SPR_DTLBMR_V);
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mtspr (SPR_DTLBTR_BASE(0) + i, ta | DTLB_PR_NOLIMIT | SPR_DTLBTR_CI);
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}
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/* Testing page */
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ea = RAM_START + (RAM_SIZE/2) + (TLB_DATA_SET_NB*PAGE_SIZE);
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ta = RAM_START + (RAM_SIZE/2) + (TLB_DATA_SET_NB*PAGE_SIZE);
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/* Write test pattern */
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REG32(ea) = 0x01234567;
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REG32(ea + PAGE_SIZE - 4) = 0x9abcdef;
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/* Set one to one translation with CI bit for testing area */
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mtspr (SPR_DTLBMR_BASE(0) + TLB_DATA_SET_NB, ea | SPR_DTLBMR_V);
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mtspr (SPR_DTLBTR_BASE(0) + TLB_DATA_SET_NB, ta | DTLB_PR_NOLIMIT | SPR_DTLBTR_CI);
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ret = lo_dtlb_ci_test(ea, TLB_DATA_SET_NB);
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ASSERT(ret == 0);
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return 0;
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}
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/* Translation address register test
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/* Translation address register test
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Set various translation and check the pattern */
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Set various translation and check the pattern */
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int itlb_translation_test (void)
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int itlb_translation_test (void)
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{
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{
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int i, j;
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int i, j;
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| Line 1120... |
Line 1166... |
immu_disable ();
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immu_disable ();
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return 0;
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return 0;
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}
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}
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/* Instruction cache inhibit bit test
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Set and clear CI bit and check the pattern. */
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int itlb_ci_test(void)
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{
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int i, j;
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unsigned long ea, ta, ret;
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/* Disable IMMU */
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immu_disable();
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/* Invalidate all entries in DTLB */
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for (i = 0; i < ITLB_WAYS; i++) {
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for (j = 0; j < ITLB_SETS; j++) {
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mtspr (SPR_ITLBMR_BASE(i) + j, 0);
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mtspr (SPR_ITLBTR_BASE(i) + j, 0);
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}
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}
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/* Set one to one translation for the use of this program */
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for (i = 0; i < TLB_TEXT_SET_NB; i++) {
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ea = FLASH_START + (i*PAGE_SIZE);
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ta = FLASH_START + (i*PAGE_SIZE);
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mtspr (SPR_ITLBMR_BASE(0) + i, ea | SPR_ITLBMR_V);
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mtspr (SPR_ITLBTR_BASE(0) + i, ta | ITLB_PR_NOLIMIT);
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}
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/* Testing page */
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ea = RAM_START + (RAM_SIZE/2) + (TLB_TEXT_SET_NB*PAGE_SIZE);
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ret = lo_itlb_ci_test (ea, TLB_TEXT_SET_NB);
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ASSERT(ret == 0);
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return 0;
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}
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int main (void)
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int main (void)
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{
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{
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int i, j;
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int i, j;
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i = j = 0; /* Get rid of warnings */
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i = j = 0; /* Get rid of warnings */
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| Line 1165... |
Line 1246... |
dtlb_premission_test (i);
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dtlb_premission_test (i);
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#else
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#else
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dtlb_premission_test (DTLB_SETS - 2);
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dtlb_premission_test (DTLB_SETS - 2);
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#endif
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#endif
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dtlb_ci_test();
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#endif
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#endif
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#if 1
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#if 1
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/* Translation test */
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/* Translation test */
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itlb_translation_test ();
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itlb_translation_test ();
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| Line 1197... |
Line 1279... |
itlb_premission_test (i);
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itlb_premission_test (i);
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#else
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#else
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itlb_premission_test (ITLB_SETS - 2);
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itlb_premission_test (ITLB_SETS - 2);
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#endif
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#endif
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itlb_ci_test();
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#endif
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#endif
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report (0xdeaddead);
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report (0xdeaddead);
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exit (0);
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exit (0);
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return 0;
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return 0;
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