Line 347... |
Line 347... |
if ((addr = mfspr(SPR_DCBLR))) {
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if ((addr = mfspr(SPR_DCBLR))) {
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mtspr(SPR_DCBLR, 0);
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mtspr(SPR_DCBLR, 0);
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}
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}
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}
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}
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/*-----------------------------------------------------[ DC configuration ]---*/
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void dc_enabled(union param_val val, void *dat)
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{
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config.dc.enabled = val.int_val;
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setsprbits (SPR_UPR, SPR_UPR_DCP, val.int_val ? 1 : 0);
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}
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void dc_nsets(union param_val val, void *dat)
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{
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if (is_power2(val.int_val) && val.int_val <= MAX_DC_SETS)
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config.dc.nsets = val.int_val;
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else {
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char tmp[200];
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sprintf (tmp, "value of power of two and lower or equal than %i expected.", MAX_DC_SETS);
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CONFIG_ERROR(tmp);
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}
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}
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void dc_nways(union param_val val, void *dat)
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{
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if (val.int_val >= 1 && val.int_val <= MAX_DC_WAYS)
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config.dc.nways = val.int_val;
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else
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CONFIG_ERROR("value 1, 2, 3 or 4 expected.");
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}
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void dc_blocksize(union param_val val, void *dat)
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{
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if (is_power2(val.int_val))
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config.dc.blocksize = val.int_val;
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else
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CONFIG_ERROR("value of power of two expected.");
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}
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void dc_ustates(union param_val val, void *dat)
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{
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if (val.int_val >= 2 && val.int_val <= 4)
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config.dc.ustates = val.int_val;
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else
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CONFIG_ERROR("invalid USTATE.");
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}
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void dc_load_missdelay(union param_val val, void *dat)
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{
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config.dc.load_missdelay = val.int_val;
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}
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void dc_load_hitdelay(union param_val val, void *dat)
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{
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config.dc.load_hitdelay = val.int_val;
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}
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void dc_store_missdelay(union param_val val, void *dat)
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{
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config.dc.store_missdelay = val.int_val;
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}
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void dc_store_hitdelay(union param_val val, void *dat)
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{
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config.dc.store_hitdelay = val.int_val;
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}
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void reg_dc_sec(void)
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{
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struct config_section *sec = reg_config_sec("dc", NULL, NULL);
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reg_config_param(sec, "enabled", paramt_int, dc_enabled);
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reg_config_param(sec, "nsets", paramt_int, dc_nsets);
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reg_config_param(sec, "nways", paramt_int, dc_nways);
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reg_config_param(sec, "blocksize", paramt_int, dc_blocksize);
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reg_config_param(sec, "ustates", paramt_int, dc_ustates);
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reg_config_param(sec, "load_missdelay", paramt_int, dc_load_missdelay);
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reg_config_param(sec, "load_hitdelay", paramt_int, dc_load_hitdelay);
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reg_config_param(sec, "store_missdelay", paramt_int, dc_store_missdelay);
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reg_config_param(sec, "store_hitdelay", paramt_int, dc_store_hitdelay);
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}
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