OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [nog_patch_47/] [or1ksim/] [cache/] [icache_model.c] - Diff between revs 1344 and 1350

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 1344 Rev 1350
Line 26... Line 26...
#include <stdio.h>
#include <stdio.h>
#include <string.h>
#include <string.h>
#include <errno.h>
#include <errno.h>
#include <stdarg.h>
#include <stdarg.h>
 
 
#include "icache_model.h"
#include "config.h"
 
 
 
#ifdef HAVE_INTTYPES_H
 
#include <inttypes.h>
 
#endif
 
 
 
#include "port.h"
 
#include "arch.h"
#include "abstract.h"
#include "abstract.h"
 
#include "icache_model.h"
#include "except.h"
#include "except.h"
#include "opcode/or32.h"
#include "opcode/or32.h"
#include "stats.h"
#include "stats.h"
#include "sim-config.h"
#include "sim-config.h"
#include "spr_defs.h"
#include "spr_defs.h"
Line 39... Line 47...
#include "sim-config.h"
#include "sim-config.h"
 
 
extern struct dev_memarea *cur_area;
extern struct dev_memarea *cur_area;
struct ic_set {
struct ic_set {
  struct {
  struct {
    unsigned long line[MAX_IC_BLOCK_SIZE];
    uint32_t line[MAX_IC_BLOCK_SIZE];
    unsigned long tagaddr;  /* tag address */
    oraddr_t tagaddr;  /* tag address */
    int lru;    /* least recently used */
    int lru;    /* least recently used */
  } way[MAX_IC_WAYS];
  } way[MAX_IC_WAYS];
} ic[MAX_IC_SETS];
} ic[MAX_IC_SETS];
 
 
void ic_info()
void ic_info()
Line 69... Line 77...
    - set 'lru' with config.ic.ustates - 1 and decrement 'lru' of other
    - set 'lru' with config.ic.ustates - 1 and decrement 'lru' of other
      ways unless they have reached 0
      ways unless they have reached 0
    - refill cache line
    - refill cache line
*/
*/
 
 
unsigned long ic_simulate_fetch(unsigned long fetchaddr)
uint32_t ic_simulate_fetch(oraddr_t fetchaddr)
{
{
  int set, way = -1;
  int set, way = -1;
  int i;
  int i;
  unsigned long tagaddr;
  oraddr_t tagaddr;
  unsigned long tmp;
  uint32_t tmp;
 
 
  /* ICache simulation enabled/disabled. */
  /* ICache simulation enabled/disabled. */
  if ((!testsprbits(SPR_UPR, SPR_UPR_ICP)) || (!testsprbits(SPR_SR, SPR_SR_ICE)) || insn_ci) {
  if ((!testsprbits(SPR_UPR, SPR_UPR_ICP)) || (!testsprbits(SPR_SR, SPR_SR_ICE)) || insn_ci) {
    tmp = evalsim_mem32(fetchaddr);
    tmp = evalsim_mem32(fetchaddr);
    if(!cur_area) {
    if(!cur_area) {
      printf("EXCEPTION: read out of memory (32-bit access to %.8lx)\n", fetchaddr);
      printf("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n",
 
             fetchaddr);
      except_handle(EXCEPT_BUSERR, cur_vadd);
      except_handle(EXCEPT_BUSERR, cur_vadd);
      return 0;
      return 0;
    }
    }
    if (!pending.valid && cur_area->log)
    if (!pending.valid && cur_area->log)
      fprintf (cur_area->log, "[%08lx] -> read %08lx\n", fetchaddr, tmp);
      fprintf (cur_area->log, "[%"PRIxADDR"] -> read %08"PRIx32"\n", fetchaddr,
 
               tmp);
    return tmp;
    return tmp;
  }
  }
 
 
  /* Which set to check out? */
  /* Which set to check out? */
  set = (fetchaddr / config.ic.blocksize) % config.ic.nsets;
  set = (fetchaddr / config.ic.blocksize) % config.ic.nsets;
Line 128... Line 138...
      tmp = ic[set].way[minway].line[((fetchaddr + i) & (config.ic.blocksize - 1)) >> 2] =
      tmp = ic[set].way[minway].line[((fetchaddr + i) & (config.ic.blocksize - 1)) >> 2] =
        evalsim_mem32((fetchaddr & ~(config.ic.blocksize - 1)) + ((fetchaddr + i) & (config.ic.blocksize - 1)));
        evalsim_mem32((fetchaddr & ~(config.ic.blocksize - 1)) + ((fetchaddr + i) & (config.ic.blocksize - 1)));
      if(!cur_area) {
      if(!cur_area) {
        ic[set].way[minway].tagaddr = -1;
        ic[set].way[minway].tagaddr = -1;
        ic[set].way[minway].lru = 0;
        ic[set].way[minway].lru = 0;
        printf("EXCEPTION: read out of memory (32-bit access to %.8lx)\n", fetchaddr);
        printf("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n",
 
               fetchaddr);
        except_handle(EXCEPT_BUSERR, cur_vadd);
        except_handle(EXCEPT_BUSERR, cur_vadd);
        return 0;
        return 0;
      }
      }
      if (!pending.valid && cur_area->log)
      if (!pending.valid && cur_area->log)
        fprintf (cur_area->log, "[%08lx] -> read %08lx\n", fetchaddr, tmp);
        fprintf (cur_area->log, "[%"PRIxADDR"] -> read %08"PRIx32"\n",
 
                 fetchaddr, tmp);
    }
    }
 
 
    ic[set].way[minway].tagaddr = tagaddr;
    ic[set].way[minway].tagaddr = tagaddr;
    for (i = 0; i < config.ic.nways; i++)
    for (i = 0; i < config.ic.nways; i++)
      if (ic[set].way[i].lru)
      if (ic[set].way[i].lru)
Line 151... Line 163...
/* First check if data is already in the cache and if it is:
/* First check if data is already in the cache and if it is:
    - invalidate block if way isn't locked
    - invalidate block if way isn't locked
   otherwise don't do anything.
   otherwise don't do anything.
*/
*/
 
 
void ic_inv(unsigned long dataaddr)
void ic_inv(oraddr_t dataaddr)
{
{
  int set, way = -1;
  int set, way = -1;
  int i;
  int i;
  unsigned long tagaddr;
  oraddr_t tagaddr;
 
 
  if (!testsprbits(SPR_UPR, SPR_UPR_ICP))
  if (!testsprbits(SPR_UPR, SPR_UPR_ICP))
    return;
    return;
 
 
  /* Which set to check out? */
  /* Which set to check out? */
Line 184... Line 196...
    ic[set].way[way].tagaddr = -1;
    ic[set].way[way].tagaddr = -1;
    ic[set].way[way].lru = 0;
    ic[set].way[way].lru = 0;
  }
  }
}
}
 
 
inline void ic_clock()
void ic_clock()
{
{
  unsigned long addr;
  oraddr_t addr;
 
 
  if ((addr = mfspr(SPR_ICBPR))) {
  if ((addr = mfspr(SPR_ICBPR))) {
    ic_simulate_fetch(addr);
    ic_simulate_fetch(addr);
    mtspr(SPR_ICBPR, 0);
    mtspr(SPR_ICBPR, 0);
  }
  }

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.