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Line 32... |
#include "abstract.h"
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#include "abstract.h"
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#include "stats.h"
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#include "stats.h"
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#include "sim-config.h"
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#include "sim-config.h"
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#include "spr_defs.h"
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#include "spr_defs.h"
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#include "sprs.h"
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#include "sprs.h"
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#include "sim-config.h"
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/* Instruction cache */
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/* Instruction cache */
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#define MAX_IC_SETS 8192
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/* Number of IC sets (power of 2) */
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#define MAX_IC_WAYS 4
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#define IC_SETS 512
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/* Block size in bytes (1, 2, 4, 8, 16, 32 etc.) */
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#define IC_BLOCK_SIZE 16
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/* Number of IC ways (1, 2, 3 etc.). */
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#define IC_WAYS 1
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/* Number of usage states (2, 3, 4 etc.). */
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#define IC_USTATES 2
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struct ic_set {
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struct ic_set {
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struct {
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struct {
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unsigned long tagaddr; /* tag address */
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unsigned long tagaddr; /* tag address */
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int lru; /* least recently used */
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int lru; /* least recently used */
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} way[IC_WAYS];
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} way[MAX_IC_WAYS];
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} ic[IC_SETS];
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} ic[MAX_IC_SETS];
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void ic_info()
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void ic_info()
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{
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{
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if (!testsprbits(SPR_UPR, SPR_UPR_ICP)) {
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if (!testsprbits(SPR_UPR, SPR_UPR_ICP)) {
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printf("ICache not implemented. Set UPR[ICP].\n");
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printf("ICache not implemented. Set UPR[ICP].\n");
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return;
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return;
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}
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}
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printf("Instruction cache %dKB: ", IC_SETS * IC_BLOCK_SIZE * IC_WAYS / 1024);
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printf("Instruction cache %dKB: ", config.ic.nsets * config.ic.blocksize * config.ic.nways / 1024);
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printf("%d ways, %d sets, block size %d bytes\n", IC_WAYS, IC_SETS, IC_BLOCK_SIZE);
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printf("%d ways, %d sets, block size %d bytes\n", config.ic.nways, config.ic.nsets, config.ic.blocksize);
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}
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}
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/* First check if instruction is already in the cache and if it is:
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/* First check if instruction is already in the cache and if it is:
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- increment IC read hit stats,
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- increment IC read hit stats,
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- set 'lru' at this way to IC_USTATES - 1 and
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- set 'lru' at this way to config.ic.ustates - 1 and
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decrement 'lru' of other ways unless they have reached 0,
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decrement 'lru' of other ways unless they have reached 0,
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and if not:
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and if not:
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- increment IC read miss stats
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- increment IC read miss stats
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- find lru way and entry and replace old tag with tag of the 'fetchaddr'
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- find lru way and entry and replace old tag with tag of the 'fetchaddr'
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- set 'lru' with IC_USTATES - 1 and decrement 'lru' of other
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- set 'lru' with config.ic.ustates - 1 and decrement 'lru' of other
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ways unless they have reached 0
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ways unless they have reached 0
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*/
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*/
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void ic_simulate_fetch(unsigned long fetchaddr)
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void ic_simulate_fetch(unsigned long fetchaddr)
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{
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{
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/* ICache simulation enabled/disabled. */
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/* ICache simulation enabled/disabled. */
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if ((!testsprbits(SPR_UPR, SPR_UPR_ICP)) || (!testsprbits(SPR_SR, SPR_SR_ICE)))
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if ((!testsprbits(SPR_UPR, SPR_UPR_ICP)) || (!testsprbits(SPR_SR, SPR_SR_ICE)))
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return;
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return;
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/* Which set to check out? */
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/* Which set to check out? */
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set = (fetchaddr / IC_BLOCK_SIZE) % IC_SETS;
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set = (fetchaddr / config.ic.blocksize) % config.ic.nsets;
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tagaddr = (fetchaddr / IC_BLOCK_SIZE) / IC_SETS;
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tagaddr = (fetchaddr / config.ic.blocksize) / config.ic.nsets;
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/* Scan all ways and try to find a matching way. */
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/* Scan all ways and try to find a matching way. */
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for (i = 0; i < IC_WAYS; i++)
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for (i = 0; i < config.ic.nways; i++)
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if (ic[set].way[i].tagaddr == tagaddr)
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if (ic[set].way[i].tagaddr == tagaddr)
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way = i;
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way = i;
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/* Did we find our cached instruction? */
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/* Did we find our cached instruction? */
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if (way >= 0) { /* Yes, we did. */
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if (way >= 0) { /* Yes, we did. */
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ic_stats.readhit++;
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ic_stats.readhit++;
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for (i = 0; i < IC_WAYS; i++)
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for (i = 0; i < config.ic.nways; i++)
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if (ic[set].way[i].lru)
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if (ic[set].way[i].lru)
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ic[set].way[i].lru--;
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ic[set].way[i].lru--;
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ic[set].way[way].lru = IC_USTATES - 1;
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ic[set].way[way].lru = config.ic.ustates - 1;
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}
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}
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else { /* No, we didn't. */
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else { /* No, we didn't. */
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int minlru = IC_USTATES - 1;
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int minlru = config.ic.ustates - 1;
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int minway = 0;
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int minway = 0;
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ic_stats.readmiss++;
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ic_stats.readmiss++;
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for (i = 0; i < IC_WAYS; i++)
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for (i = 0; i < config.ic.nways; i++)
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if (ic[set].way[i].lru < minlru)
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if (ic[set].way[i].lru < minlru)
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minway = i;
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minway = i;
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ic[set].way[minway].tagaddr = tagaddr;
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ic[set].way[minway].tagaddr = tagaddr;
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for (i = 0; i < IC_WAYS; i++)
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for (i = 0; i < config.ic.nways; i++)
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if ((ic[set].way[i].lru) &&
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if ((ic[set].way[i].lru) &&
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(getsprbits(SPR_ICCR, SPR_ICCR_EW) & (1 << i)))
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(getsprbits(SPR_ICCR, SPR_ICCR_EW) & (1 << i)))
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ic[set].way[i].lru--;
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ic[set].way[i].lru--;
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ic[set].way[minway].lru = IC_USTATES - 1;
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ic[set].way[minway].lru = config.ic.ustates - 1;
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}
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}
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}
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}
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/* First check if data is already in the cache and if it is:
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/* First check if data is already in the cache and if it is:
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- invalidate block if way isn't locked
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- invalidate block if way isn't locked
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Line 129... |
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if (!testsprbits(SPR_UPR, SPR_UPR_ICP))
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if (!testsprbits(SPR_UPR, SPR_UPR_ICP))
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return;
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return;
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/* Which set to check out? */
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/* Which set to check out? */
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set = (dataaddr / IC_BLOCK_SIZE) % IC_SETS;
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set = (dataaddr / config.ic.blocksize) % config.ic.nsets;
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tagaddr = (dataaddr / IC_BLOCK_SIZE) / IC_SETS;
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tagaddr = (dataaddr / config.ic.blocksize) / config.ic.nsets;
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/* Scan all ways and try to find a matching way. */
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/* Scan all ways and try to find a matching way. */
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for (i = 0; i < IC_WAYS; i++)
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for (i = 0; i < config.ic.nways; i++)
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if (ic[set].way[i].tagaddr == tagaddr)
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if (ic[set].way[i].tagaddr == tagaddr)
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way = i;
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way = i;
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/* Did we find our cached data? */
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/* Did we find our cached data? */
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if ((way >= 0) && (getsprbits(SPR_ICCR, SPR_ICCR_EW) & (1 << way))) { /* Yes, we did. */
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if ((way >= 0) && (getsprbits(SPR_ICCR, SPR_ICCR_EW) & (1 << way))) { /* Yes, we did. */
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