| Line 84... |
Line 84... |
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/* Calls IMMU translation routines before simulating insn
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/* Calls IMMU translation routines before simulating insn
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cache for virtually indexed insn cache or after simulating insn cache
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cache for virtually indexed insn cache or after simulating insn cache
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for physically indexed insn cache. It returns physical address. */
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for physically indexed insn cache. It returns physical address. */
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unsigned long simulate_ic_mmu_fetch(unsigned long virtaddr)
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static inline unsigned long simulate_ic_mmu_fetch(unsigned long virtaddr)
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{
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{
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unsigned long phyaddr;
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unsigned long phyaddr;
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if ((phyaddr = translate_vrt_to_phy_add(virtaddr, 0)) != -1) {
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if ((phyaddr = translate_vrt_to_phy_add(virtaddr, 0)) != -1) {
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| Line 104... |
Line 104... |
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/* Calls DMMU translation routines (load cycles) before simulating data
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/* Calls DMMU translation routines (load cycles) before simulating data
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cache for virtually indexed data cache or after simulating data cache
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cache for virtually indexed data cache or after simulating data cache
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for physically indexed data cache. It returns physical address. */
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for physically indexed data cache. It returns physical address. */
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unsigned long simulate_dc_mmu_load(unsigned long virtaddr)
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static inline unsigned long simulate_dc_mmu_load(unsigned long virtaddr)
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{
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{
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if (config.dc.tagtype == CT_NONE)
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if (config.dc.tagtype == CT_NONE)
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return dmmu_translate(virtaddr, 0);
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return dmmu_translate(virtaddr, 0);
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else
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else
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if (config.dc.tagtype == CT_VIRTUAL) {
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if (config.dc.tagtype == CT_VIRTUAL) {
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| Line 130... |
Line 130... |
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/* Calls DMMU translation routines (store cycles) before simulating data
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/* Calls DMMU translation routines (store cycles) before simulating data
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cache for virtually indexed data cache or after simulating data cache
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cache for virtually indexed data cache or after simulating data cache
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for physically indexed data cache. It returns physical address. */
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for physically indexed data cache. It returns physical address. */
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unsigned long simulate_dc_mmu_store(unsigned long virtaddr)
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static inline unsigned long simulate_dc_mmu_store(unsigned long virtaddr)
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{
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{
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if (config.dc.tagtype == CT_NONE)
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if (config.dc.tagtype == CT_NONE)
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return dmmu_translate(virtaddr, 0);
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return dmmu_translate(virtaddr, 0);
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else
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else
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if (config.dc.tagtype == CT_VIRTUAL) {
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if (config.dc.tagtype == CT_VIRTUAL) {
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| Line 368... |
Line 368... |
struct dev_memarea *dev;
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struct dev_memarea *dev;
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if (config.sim.mprofile)
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if (config.sim.mprofile)
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mprofile (memaddr, MPROF_32 | MPROF_READ);
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mprofile (memaddr, MPROF_32 | MPROF_READ);
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cur_vadd = memaddr;
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if (config.dmmu.enabled)
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memaddr = simulate_dc_mmu_load(memaddr);
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if (pending.valid)
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return 0;
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if (memaddr & 3) {
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if (memaddr & 3) {
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except_handle (EXCEPT_ALIGN, memaddr);
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except_handle (EXCEPT_ALIGN, memaddr);
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return 0;
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return 0;
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}
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}
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cur_vadd = memaddr;
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memaddr = simulate_dc_mmu_load(memaddr);
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if (pending.valid)
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return 0;
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if (config.debug.enabled)
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if (config.debug.enabled)
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*breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */
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*breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */
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temp = evalsim_mem32(memaddr);
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temp = evalsim_mem32(memaddr);
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if (config.debug.enabled)
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if (config.debug.enabled)
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*breakpoint += CheckDebugUnit(DebugLoadData,temp); /* MM170901 */
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*breakpoint += CheckDebugUnit(DebugLoadData,temp); /* MM170901 */
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| Line 415... |
Line 414... |
unsigned short temp;
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unsigned short temp;
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if (config.sim.mprofile)
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if (config.sim.mprofile)
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mprofile (memaddr, MPROF_16 | MPROF_READ);
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mprofile (memaddr, MPROF_16 | MPROF_READ);
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cur_vadd = memaddr;
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if (config.dmmu.enabled)
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memaddr = simulate_dc_mmu_load(memaddr);
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if (pending.valid)
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return 0;
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|
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if (memaddr & 1) {
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if (memaddr & 1) {
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except_handle (EXCEPT_ALIGN, memaddr);
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except_handle (EXCEPT_ALIGN, memaddr);
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return 0;
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return 0;
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}
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}
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|
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cur_vadd = memaddr;
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memaddr = simulate_dc_mmu_load(memaddr);
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if (pending.valid)
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return 0;
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if (config.debug.enabled)
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if (config.debug.enabled)
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*breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */
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*breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */
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temp = evalsim_mem16(memaddr);
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temp = evalsim_mem16(memaddr);
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if (config.debug.enabled)
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if (config.debug.enabled)
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| Line 445... |
Line 443... |
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if (config.sim.mprofile)
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if (config.sim.mprofile)
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mprofile (memaddr, MPROF_8 | MPROF_READ);
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mprofile (memaddr, MPROF_8 | MPROF_READ);
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|
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cur_vadd = memaddr;
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cur_vadd = memaddr;
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if (config.dmmu.enabled)
|
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memaddr = simulate_dc_mmu_load(memaddr);
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memaddr = simulate_dc_mmu_load(memaddr);
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if (pending.valid)
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if (pending.valid)
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return 0;
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return 0;
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|
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if (config.debug.enabled)
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if (config.debug.enabled)
|
*breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */
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*breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */
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|
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temp = evalsim_mem8(memaddr);
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temp = evalsim_mem8(memaddr);
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if (config.debug.enabled)
|
if (config.debug.enabled)
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| Line 465... |
Line 463... |
void set_mem32(unsigned long memaddr, unsigned long value,int* breakpoint)
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void set_mem32(unsigned long memaddr, unsigned long value,int* breakpoint)
|
{
|
{
|
if (config.sim.mprofile)
|
if (config.sim.mprofile)
|
mprofile (memaddr, MPROF_32 | MPROF_WRITE);
|
mprofile (memaddr, MPROF_32 | MPROF_WRITE);
|
|
|
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if (memaddr & 3) {
|
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except_handle (EXCEPT_ALIGN, memaddr);
|
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return;
|
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}
|
|
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cur_vadd = memaddr;
|
cur_vadd = memaddr;
|
if (config.dmmu.enabled)
|
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memaddr = simulate_dc_mmu_store(memaddr);
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memaddr = simulate_dc_mmu_store(memaddr);
|
|
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/* If we produced exception don't set anything */
|
/* If we produced exception don't set anything */
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if (pending.valid)
|
if (pending.valid)
|
return;
|
return;
|
|
|
if (memaddr & 3) {
|
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except_handle (EXCEPT_ALIGN, memaddr);
|
|
return;
|
|
}
|
|
|
|
if (config.debug.enabled) {
|
if (config.debug.enabled) {
|
*breakpoint += CheckDebugUnit(DebugStoreAddress,memaddr); /* 28/05/01 CZ */
|
*breakpoint += CheckDebugUnit(DebugStoreAddress,memaddr); /* 28/05/01 CZ */
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*breakpoint += CheckDebugUnit(DebugStoreData,value);
|
*breakpoint += CheckDebugUnit(DebugStoreData,value);
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}
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}
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|
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| Line 524... |
Line 520... |
void set_mem16(unsigned long memaddr, unsigned short value,int* breakpoint)
|
void set_mem16(unsigned long memaddr, unsigned short value,int* breakpoint)
|
{
|
{
|
if (config.sim.mprofile)
|
if (config.sim.mprofile)
|
mprofile (memaddr, MPROF_16 | MPROF_WRITE);
|
mprofile (memaddr, MPROF_16 | MPROF_WRITE);
|
|
|
|
if (memaddr & 1) {
|
|
except_handle (EXCEPT_ALIGN, memaddr);
|
|
return;
|
|
}
|
|
|
cur_vadd = memaddr;
|
cur_vadd = memaddr;
|
if (config.dmmu.enabled)
|
|
memaddr = simulate_dc_mmu_store(memaddr);
|
memaddr = simulate_dc_mmu_store(memaddr);
|
|
|
/* If we produced exception don't set anything */
|
/* If we produced exception don't set anything */
|
if (pending.valid)
|
if (pending.valid)
|
return;
|
return;
|
|
|
if (memaddr & 1) {
|
|
except_handle (EXCEPT_ALIGN, memaddr);
|
|
return;
|
|
}
|
|
|
|
if (config.debug.enabled) {
|
if (config.debug.enabled) {
|
*breakpoint += CheckDebugUnit(DebugStoreAddress,memaddr); /* 28/05/01 CZ */
|
*breakpoint += CheckDebugUnit(DebugStoreAddress,memaddr); /* 28/05/01 CZ */
|
*breakpoint += CheckDebugUnit(DebugStoreData,value);
|
*breakpoint += CheckDebugUnit(DebugStoreData,value);
|
}
|
}
|
|
|
| Line 582... |
Line 576... |
{
|
{
|
if (config.sim.mprofile)
|
if (config.sim.mprofile)
|
mprofile (memaddr, MPROF_8 | MPROF_WRITE);
|
mprofile (memaddr, MPROF_8 | MPROF_WRITE);
|
|
|
cur_vadd = memaddr;
|
cur_vadd = memaddr;
|
if (config.dmmu.enabled)
|
|
memaddr = simulate_dc_mmu_store(memaddr);
|
memaddr = simulate_dc_mmu_store(memaddr);
|
|
|
/* If we produced exception don't set anything */
|
/* If we produced exception don't set anything */
|
if (pending.valid) return;
|
if (pending.valid) return;
|
|
|
if (config.debug.enabled) {
|
if (config.debug.enabled) {
|
*breakpoint += CheckDebugUnit(DebugStoreAddress,memaddr); /* 28/05/01 CZ */
|
*breakpoint += CheckDebugUnit(DebugStoreAddress,memaddr); /* 28/05/01 CZ */
|
