| Line 40... |
Line 40... |
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/* Benchmark multi issue execution */
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/* Benchmark multi issue execution */
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int multissue[20];
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int multissue[20];
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int supercycles;
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int supercycles;
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/* Load and store stalls */
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int loadcycles, storecycles;
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/* Result forwarding stall cycles */
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int forwardingcycles;
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/* Completition queue */
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/* Completition queue */
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struct icomplet_entry icomplet[20];
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struct icomplet_entry icomplet[20];
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/* Program counter */
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/* Program counter */
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unsigned long pc;
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unsigned long pc;
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| Line 234... |
Line 240... |
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void reset()
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void reset()
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{
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{
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cycles = 0;
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cycles = 0;
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supercycles = 0;
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supercycles = 0;
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loadcycles = 0;
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storecycles = 0;
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forwardingcycles = 0;
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memset(reg, 0, sizeof(reg));
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memset(reg, 0, sizeof(reg));
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memset(iqueue, 0, sizeof(iqueue));
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memset(iqueue, 0, sizeof(iqueue));
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memset(icomplet, 0, sizeof(icomplet));
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memset(icomplet, 0, sizeof(icomplet));
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pctemp = eval_label("_main");
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pctemp = eval_label("_main");
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pc = pctemp;
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pc = pctemp;
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| Line 247... |
Line 256... |
void fetch()
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void fetch()
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{
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{
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/* Cycles after reset. */
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/* Cycles after reset. */
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cycles++;
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cycles++;
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/* Simulate instruction cache */
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ic_simulate(pc);
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/* Fetch instruction. */
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/* Fetch instruction. */
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strcpy(iqueue[0].insn, mem[pc].insn);
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strcpy(iqueue[0].insn, mem[pc].insn);
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strcpy(iqueue[0].op1, mem[pc].op1);
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strcpy(iqueue[0].op1, mem[pc].op1);
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strcpy(iqueue[0].op2, mem[pc].op2);
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strcpy(iqueue[0].op2, mem[pc].op2);
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strcpy(iqueue[0].op3, mem[pc].op3);
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strcpy(iqueue[0].op3, mem[pc].op3);
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| Line 618... |
Line 630... |
set_operand(cur->op1, 1);
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set_operand(cur->op1, 1);
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else
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else
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set_operand(cur->op1, 0);
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set_operand(cur->op1, 0);
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} else
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} else
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if (strcmp(cur->insn, "simrdtsc") == 0) {
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if (strcmp(cur->insn, "simrdtsc") == 0) {
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set_operand(cur->op1, supercycles);
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set_operand(cur->op1, cycles+loadcycles+storecycles+forwardingcycles);
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} else
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} else
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if (strcmp(cur->insn, "simprintf") == 0) {
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if (strcmp(cur->insn, "simprintf") == 0) {
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unsigned long stackaddr;
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unsigned long stackaddr;
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stackaddr = eval_reg(FRAME_REG);
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stackaddr = eval_reg(FRAME_REG);
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| Line 641... |
Line 653... |
addfstats(icomplet[0].func_unit, iqueue[0].func_unit, 1, check_depend());
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addfstats(icomplet[0].func_unit, iqueue[0].func_unit, 1, check_depend());
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/* Dynamic, single stats. */
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/* Dynamic, single stats. */
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addsstats(iqueue[0].insn, 1, 0);
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addsstats(iqueue[0].insn, 1, 0);
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if (cur->func_unit == store)
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storecycles += 0;
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if (cur->func_unit == load)
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loadcycles += 0;
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if (check_depend())
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forwardingcycles += 0;
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/* Pseudo multiple issue benchmark */
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/* Pseudo multiple issue benchmark */
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if ((multissue[cur->func_unit] == 0) || (check_depend())) {
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if ((multissue[cur->func_unit] == 0) || (check_depend())) {
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int i;
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int i;
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for (i = 0; i < 20; i++)
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for (i = 0; i < 20; i++)
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multissue[i] = 1;
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multissue[i] = 9;
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supercycles++;
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supercycles++;
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multissue[arith] = 2;
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multissue[arith] = 9;
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multissue[store] = 2;
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multissue[store] = 9;
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multissue[load] = 2;
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multissue[load] = 9;
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}
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}
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multissue[cur->func_unit]--;
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multissue[cur->func_unit]--;
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return;
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return;
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}
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}
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| Line 717... |
Line 738... |
{
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{
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int i;
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int i;
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printf("\n\nIQ[0]:");
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printf("\n\nIQ[0]:");
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dumpmemory(iqueue[0].insn_addr, iqueue[0].insn_addr + 4);
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dumpmemory(iqueue[0].insn_addr, iqueue[0].insn_addr + 4);
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printf(" (just executed)\tCYCLE: %u \tSUPERCYCLE: %u\nPC:", cycles, supercycles);
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printf(" (just executed)\tCYCLES: %u \nSuperscalar CYCLES: %u\n", cycles, supercycles);
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printf("Additional LOAD CYCLES: %u STORE CYCLES: %u\n", loadcycles, storecycles);
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printf("Additional RESULT FORWARDING CYCLES: %u\nPC:", forwardingcycles);
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dumpmemory(pc, pc + 4);
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dumpmemory(pc, pc + 4);
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printf(" (next insn)");
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printf(" (next insn)");
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for(i = 0; i < MAX_GPRS; i++) {
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for(i = 0; i < MAX_GPRS; i++) {
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if (i % 4 == 0)
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if (i % 4 == 0)
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printf("\n");
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printf("\n");
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