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Line 34... |
#include "sprs.h"
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#include "sprs.h"
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#include "sim-config.h"
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#include "sim-config.h"
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#include "debug_unit.h"
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#include "debug_unit.h"
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#include "execute.h"
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#include "execute.h"
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extern int cont_run;
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extern struct iqueue_entry iqueue[20];
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extern unsigned long pc_phy;
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extern struct iqueue_entry iqueue[];
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extern int delay_insn;
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extern int delay_insn;
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extern oraddr_t pcprev;
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extern oraddr_t pcdelay;
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int except_pending = 0;
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struct _pending pending;
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static const char *except_names[] = {
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NULL,
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"Reset",
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"Bus Error",
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"Data Page Fault",
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"Insn Page Fault",
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"Tick timer",
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"Alignment",
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"Illegal instruction",
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"Interrupt",
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"Data TLB Miss",
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"Insn TLB Miss",
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"Range",
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"System Call",
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"Trap" };
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/* Discards all pending exceptions */
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static const char *except_name(oraddr_t except)
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void clear_pending_exception()
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{
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{
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pending.valid = 0;
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return except_names[except >> 8];
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pending.type = 0;
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pending.address = 0;
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pending.saved = 0;
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}
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}
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/* Asserts OR1K exception. */
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/* Asserts OR1K exception. */
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void except_handle(oraddr_t except, oraddr_t ea)
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void except_handle(oraddr_t except, oraddr_t ea)
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{
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{
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if(debug_ignore_exception (except)) {
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if(debug_ignore_exception (except))
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clear_pending_exception ();
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return;
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} else {
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pending.valid = 1;
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except_pending = 1;
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pending.type = except;
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pending.address = ea;
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if (delay_insn)
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pending.saved = pc - 4;
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else
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pending.saved = pc;
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if (config.sim.verbose)
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if (config.sim.verbose)
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PRINTF("Exception 0x%"PRIxADDR" (%s) at 0x%"PRIxADDR", EA: 0x%"PRIxADDR
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PRINTF("Exception 0x%"PRIxADDR" (%s) at 0x%"PRIxADDR", EA: 0x%"PRIxADDR
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", ppc: 0x%"PRIxADDR", npc: 0x%"PRIxADDR", cycles %lld, #%lld\n",
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", ppc: 0x%"PRIxADDR", npc: 0x%"PRIxADDR", dpc: 0x%"PRIxADDR
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except, EXCEPT_NAME(except), iqueue[0].insn_addr, ea, pc, pcnext,
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", cycles %lld, #%lld\n",
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except, except_name(except), pcprev, ea, pc, pcnext, pcdelay,
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runtime.sim.cycles, runtime.cpu.instructions);
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runtime.sim.cycles, runtime.cpu.instructions);
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}
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}
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/* Actually handles exception */
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pcnext = except + (testsprbits (SPR_SR, SPR_SR_EPH) ? 0xf0000000 : 0x00000000);
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void except_handle_backend (oraddr_t except, oraddr_t ea, oraddr_t pc_saved)
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{
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#if ONLY_VIRTUAL_MACHINE
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fprintf(stderr, "WARNING: No exception processing while ONLY_VIRTUAL_MACHINE is defined.\n");
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cont_run = 0;
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#else
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if (delay_insn) {
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if (config.sim.verbose) PRINTF("INFO: Exception during execution of delay slot insn.\n");
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pc -= 4;
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}
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pc_saved = pc & ~ADDR_C(0x3);
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switch(except) {
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if (except == EXCEPT_ILLEGAL)
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/* EPCR is irrelevent */
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mtspr(SPR_EPCR_BASE, pending.saved);
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case EXCEPT_RESET:
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else if (except == EXCEPT_ALIGN)
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break;
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mtspr(SPR_EPCR_BASE, pending.saved);
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/* EPCR is loaded with address of instruction that caused the exception */
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else if (except == EXCEPT_DTLBMISS)
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/* All these exceptions happen during a simulated instruction */
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mtspr(SPR_EPCR_BASE, pending.saved);
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case EXCEPT_BUSERR:
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else if (except == EXCEPT_DPF)
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case EXCEPT_DPF:
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mtspr(SPR_EPCR_BASE, pending.saved);
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case EXCEPT_IPF:
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else if (except == EXCEPT_BUSERR)
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case EXCEPT_ALIGN:
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mtspr(SPR_EPCR_BASE, pending.saved);
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case EXCEPT_ILLEGAL:
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else if (except == EXCEPT_TRAP)
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case EXCEPT_DTLBMISS:
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mtspr(SPR_EPCR_BASE, pending.saved);
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case EXCEPT_ITLBMISS:
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else if (except == EXCEPT_RANGE)
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case EXCEPT_RANGE:
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mtspr(SPR_EPCR_BASE, pending.saved);
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case EXCEPT_TRAP:
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else if (except == EXCEPT_ITLBMISS)
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mtspr(SPR_EPCR_BASE, pc - (delay_insn ? 4 : 0));
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mtspr(SPR_EPCR_BASE, pending.saved);
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break;
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else if (except == EXCEPT_IPF)
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/* EPCR is loaded with address of next not-yet-executed instruction */
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mtspr(SPR_EPCR_BASE, pending.saved);
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case EXCEPT_SYSCALL:
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else
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mtspr(SPR_EPCR_BASE, (pc + 4) - (delay_insn ? 4 : 0));
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mtspr(SPR_EPCR_BASE, pc_saved);
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break;
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/* These exceptions happen AFTER (or before) an instruction has been
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* simulated, therefore the pc already points to the *next* instruction */
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case EXCEPT_TICK:
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case EXCEPT_INT:
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mtspr(SPR_EPCR_BASE, pc - (delay_insn ? 4 : 0));
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/* If we don't update the pc now, then it will only happen *after* the next
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* instruction (There would be serious problems if the next instruction just
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* happens to be a branch), when it should happen NOW. */
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pc = pcnext;
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pcnext += 4;
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break;
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}
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mtspr(SPR_EEAR_BASE, ea);
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mtspr(SPR_EEAR_BASE, ea);
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mtspr(SPR_ESR_BASE, mfspr(SPR_SR));
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mtspr(SPR_ESR_BASE, mfspr(SPR_SR));
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/* Address translation is always disabled when starting exception. */
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/* Address translation is always disabled when starting exception. */
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Line 124... |
mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_OVE); /* Disable overflow flag exception. */
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mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_OVE); /* Disable overflow flag exception. */
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mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_SM); /* SUPV mode */
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mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_SM); /* SUPV mode */
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mtspr(SPR_SR, mfspr(SPR_SR) & ~(SPR_SR_IEE | SPR_SR_TEE)); /* Disable interrupts. */
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mtspr(SPR_SR, mfspr(SPR_SR) & ~(SPR_SR_IEE | SPR_SR_TEE)); /* Disable interrupts. */
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clear_pending_exception ();
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delay_insn = 0;
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pc = (unsigned long)except + (testsprbits (SPR_SR, SPR_SR_EPH) ? 0xf0000000 : 0x00000000);
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/* This has been removed. All exceptions (not just SYSCALL) suffer
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from the same problem. The solution is to continue just like
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the pipeline would, and issue the exception on the next
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clock cycle. We assume now that this function is being called
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->BEFORE<- the instruction fetch and after the previous update
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which always yields the correct behavior. This has the added
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advantage that a debugger can prevent an exception from
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taking place by resetting the pc. */
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#if 0
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/* MM: We do pc update after the execute (in the simulator), so we
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decrease it by 4 so that next instruction points to first exception
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instruction. Do NOT comment this out. */
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if (except == EXCEPT_SYSCALL)
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pc -= 4;
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#endif
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pcnext = pc + 4;
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/* Added by CZ 27/05/01 */
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pc_phy = pc; /* An exception always turns off the MMU, so
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pc is always pc_phy */
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#endif /* !ONLY_VIRUAL_MACHINE */
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}
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}
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