| Line 165... |
Line 165... |
mtspr(SPR_SR, mfspr(SPR_SR) & ~(SPR_SR_DME));
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mtspr(SPR_SR, mfspr(SPR_SR) & ~(SPR_SR_DME));
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mtspr(SPR_SR, mfspr(SPR_SR) & ~(SPR_SR_IME));
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mtspr(SPR_SR, mfspr(SPR_SR) & ~(SPR_SR_IME));
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|
|
mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_SUPV); /* SUPV mode */
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mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_SUPV); /* SUPV mode */
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mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_EXR); /* Disable except. */
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mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_EXR); /* Disable except. */
|
|
|
pc = (unsigned long)except;
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pc = (unsigned long)except;
|
|
|
/* This has been removed. All exceptions (not just SYSCALL) suffer
|
/* This has been removed. All exceptions (not just SYSCALL) suffer
|
from the same problem. The solution is to continue just like
|
from the same problem. The solution is to continue just like
|
the pipeline would, and issue the exception on the next
|
the pipeline would, and issue the exception on the next
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| Line 178... |
Line 179... |
advantage that a debugger can prevent an exception from
|
advantage that a debugger can prevent an exception from
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taking place by resetting the pc. */
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taking place by resetting the pc. */
|
#if 0
|
#if 0
|
/* MM: We do pc update after the execute (in the simulator), so we
|
/* MM: We do pc update after the execute (in the simulator), so we
|
decrease it by 4 so that next instruction points to first exception
|
decrease it by 4 so that next instruction points to first exception
|
instruction. */
|
instruction. Do NOT comment this out. */
|
if (except == EXCEPT_SYSCALL)
|
if (except == EXCEPT_SYSCALL)
|
pc -= 4;
|
pc -= 4;
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#endif
|
#endif
|
|
|
pcnext = pc+4;
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pcnext = pc+4;
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|
|
/* Added by CZ 27/05/01 */
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/* Added by CZ 27/05/01 */
|
pc_phy = pc; /* An exception always turns off the MMU, so
|
pc_phy = pc; /* An exception always turns off the MMU, so
|
pc is always pc_phy */
|
pc is always pc_phy */
|
