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[/] [or1k/] [tags/] [nog_patch_47/] [or1ksim/] [cpu/] [or1k/] [except.c] - Diff between revs 464 and 479

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Rev 464 Rev 479
Line 24... Line 24...
#include "abstract.h"
#include "abstract.h"
#include "except.h"
#include "except.h"
#include "sprs.h"
#include "sprs.h"
#include "sim-config.h"
#include "sim-config.h"
 
 
static void except_handle_backend(int,unsigned long,unsigned long);
 
 
 
extern int cont_run;
extern int cont_run;
extern struct iqueue_entry iqueue[20];
extern struct iqueue_entry iqueue[20];
extern unsigned long pc;
extern unsigned long pc;
extern unsigned long pcnext;
extern unsigned long pcnext;
extern unsigned long pc_phy;
extern unsigned long pc_phy;
Line 38... Line 36...
extern int delay_insn;
extern int delay_insn;
int cycle_delay = 0;  /* Added by CZ 27/05/01 */
int cycle_delay = 0;  /* Added by CZ 27/05/01 */
 
 
struct _pending pending;
struct _pending pending;
 
 
void ClearPendingException()
/* Discards all pending exceptions */
{
void clear_pending_exception()
  if(pending.valid && pending.type != EXCEPT_RESET)
 
    {
    {
      pending.valid = 0;
      pending.valid = 0;
      pending.type = 0;
      pending.type = 0;
      pending.address = 0;
      pending.address = 0;
      pending.saved = 0;
      pending.saved = 0;
    }
    }
}
 
 
 
/* The delayed_pc and delayed_pcnext are fields which hold
 
   the original value of the PC across breakpoint exceptions
 
   in the case of a development interface. Due to an implementation
 
   issues, DIR injected instructions can modify these values
 
   when in fact they should not. So we save and restore them
 
   later on. */
 
static unsigned long delayed_pc = 0;
 
static unsigned long delayed_pcnext = 0;
 
static int delayed_pc_valid = 0;
 
 
 
void ClearPreparedPCState()
 
{
 
  delayed_pc_valid = 0;
 
}
 
 
 
/* This routine is never called if the cpu is not stalled...
 
   i.e. cpu_stalled == 0. _execute_update_pc is called
 
   directly in that case. This routine exists to sort out
 
   the difference between a single step break and a full
 
   software break. */
 
void PrepareExceptionPC(unsigned long t_pc,unsigned long t_pcnext)
 
{
 
  /* If a real exception occurred which has stalled
 
     the CPU, we are expecting to halt before the end
 
     of the instruction. Otherwise, if it is a single
 
     step that has caused the halt, we are expected to
 
     complete the entire instruction and stop after
 
     it is finished. */
 
 
 
  if(pending.valid)
/* Asserts OR1K exception. */
    {
 
      delayed_pc = t_pc;
 
      delayed_pcnext = t_pcnext;
 
      delayed_pc_valid = 1;
 
    }
 
  else
 
    _execute_update_pc(t_pc,t_pcnext);
 
}
 
 
 
void PrepareException()
 
{
 
  if(delayed_pc_valid)
 
    {
 
      pc = delayed_pc;
 
      pcnext = delayed_pcnext;
 
      pc_phy = simulate_ic_mmu_fetch(pc);
 
      if (verify_memoryarea(pc_phy))
 
              except_handle(EXCEPT_BUSERR, pc);
 
      delayed_pc_valid = delayed_pc = delayed_pcnext = 0;
 
    }
 
 
 
  if(pending.valid)
 
    except_handle_backend(pending.type,pending.address,pending.saved);
 
}
 
 
 
/* Handle OR1K exceptions. */
 
void except_handle(int except, unsigned long ea)
void except_handle(int except, unsigned long ea)
{
{
 
  if(debug_ignore_exception (except)) {
 
    clear_pending_exception ();
 
  } else {
  pending.valid = 1;
  pending.valid = 1;
  pending.type = except;
  pending.type = except;
  pending.address = ea;
  pending.address = ea;
  if (delay_insn)
  if (delay_insn)
    pending.saved = pc - 4;
    pending.saved = pc - 4;
  else
  else
    pending.saved = pc;
    pending.saved = pc;
 
    printf("Exception 0x%x (%s): insn_addr 0x%x, EA 0x%x, pc: 0x%x, pcnext: 0x%x\n",
  if(DebugCheckException(except))
      except, EXCEPT_NAME(except), iqueue[0].insn_addr, ea, pc, pcnext);
    {
 
      pending.valid = 0;
 
      pending.type = 0;
 
      pending.address = 0;
 
      pending.saved = 0;
 
    }
 
  else
 
    {
 
      printf("Exception 0x%x (%s): ", except, EXCEPT_NAME(except));
 
      printf("Iqueue[0].insn_addr: 0x%x  Eff ADDR: 0x%x\n",  iqueue[0].insn_addr, ea);
 
      printf("  pc: 0x%x  pcnext: 0x%x\n",  pc, pcnext);
 
    }
    }
 
 
  cycle_delay = 0;  /* An exception stalls the CPU 0 clock cycles */
  cycle_delay = 0;  /* An exception stalls the CPU 0 clock cycles */
}
}
 
 
static void except_handle_backend(int except, unsigned long ea, unsigned long pc_saved)
/* Actually handles exception */
 
void except_handle_backend (int except, unsigned long ea, unsigned long pc_saved)
{
{
  /* Ignore masked exceptions */
  /* Ignore masked exceptions */
  if (! IS_NME(except) && (!(mfspr(SPR_SR) & SPR_SR_EXR))) {
  if (! IS_NME(except) && (!(mfspr(SPR_SR) & SPR_SR_EXR))) {
    if (config.sim.verbose)
    if (config.sim.verbose)
                  printf("INFO: Exception occured while exception detection was disabled.\n");
                  printf("INFO: Exception occured while exception detection was disabled.\n");
Line 189... Line 123...
        mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_OVE);     /* Disable overflow flag exception. */
        mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_OVE);     /* Disable overflow flag exception. */
 
 
        mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_SUPV);     /* SUPV mode */
        mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_SUPV);     /* SUPV mode */
        mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_EIR);     /* Disable interrupts. */
        mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_EIR);     /* Disable interrupts. */
 
 
  pending.valid = 0;
  clear_pending_exception ();
  pending.type = 0;
 
  pending.address = 0;
 
  pending.saved = 0;
 
 
 
        pc = (unsigned long)except;
        pc = (unsigned long)except;
 
 
        /* This has been removed. All exceptions (not just SYSCALL) suffer
        /* This has been removed. All exceptions (not just SYSCALL) suffer
           from the same problem. The solution is to continue just like
           from the same problem. The solution is to continue just like

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