OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [nog_patch_47/] [or1ksim/] [cpu/] [or1k/] [except.c] - Diff between revs 535 and 556

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 535 Rev 556
Line 122... Line 122...
  mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_SUPV);   /* SUPV mode */
  mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_SUPV);   /* SUPV mode */
  mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_EIR);   /* Disable interrupts. */
  mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_EIR);   /* Disable interrupts. */
 
 
  clear_pending_exception ();
  clear_pending_exception ();
 
 
  pc = (unsigned long)except;
  pc = (unsigned long)except + (testsprbits (SPR_SR, SPR_SR_EP) ? 0xf0000000 : 0x00000000);
 
 
  /* This has been removed. All exceptions (not just SYSCALL) suffer
  /* This has been removed. All exceptions (not just SYSCALL) suffer
     from the same problem. The solution is to continue just like
     from the same problem. The solution is to continue just like
     the pipeline would, and issue the exception on the next
     the pipeline would, and issue the exception on the next
     clock cycle. We assume now that this function is being called
     clock cycle. We assume now that this function is being called
Line 145... Line 145...
 
 
  /* Added by CZ 27/05/01 */
  /* Added by CZ 27/05/01 */
  pc_phy = pc;      /* An exception always turns off the MMU, so
  pc_phy = pc;      /* An exception always turns off the MMU, so
           pc is always pc_phy */
           pc is always pc_phy */
 
 
#endif
#endif /* !ONLY_VIRUAL_MACHINE */
}
}
 
 
 No newline at end of file
 No newline at end of file

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.