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https://opencores.org/ocsvn/or1k/or1k/trunk
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| Rev 51 |
Rev 64 |
| Line 49... |
Line 49... |
fetch(); /* before starting with exception.*/
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fetch(); /* before starting with exception.*/
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decode(&iqueue[0]);
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decode(&iqueue[0]);
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execute();
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execute();
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}
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}
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/* cont_run = 0; */
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if (!(mfspr(SPR_SR) & SPR_SR_EXR)) {
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if (!(mfspr(SPR_SR) & SPR_SR_EXR)) {
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printf("ABORT: Exception occured while exception detection was disabled.\n");
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printf("ABORT: Exception occured while exception detection was disabled.\n");
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cont_run = 0;
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cont_run = 0;
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return;
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return;
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}
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}
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pc_saved = (pc & ~0x3) |
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pc_saved = pc & ~0x3;
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(mfspr(SPR_SR) & (SPR_SR_SUPV | SPR_SR_EXR));
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mtspr(SPR_EPCR_BASE, pc_saved);
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mtspr(SPR_EPCR_BASE, pc_saved);
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mtspr(SPR_EEAR_BASE, ea);
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mtspr(SPR_EEAR_BASE, ea);
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mtspr(SPR_ESR_BASE, mfspr(SPR_SR));
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/* Address translation is always disabled when starting exception. */
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mtspr(SPR_SR, mfspr(SPR_SR) & ~(SPR_SR_DME));
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mtspr(SPR_SR, mfspr(SPR_SR) & ~(SPR_SR_IME));
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mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_SUPV); /* SUPV mode */
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mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_SUPV); /* SUPV mode */
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mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_EXR); /* Disable except. */
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mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_EXR); /* Disable except. */
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pc = (unsigned long)except;
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pc = (unsigned long)except;
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pctemp = (unsigned long)except;
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pctemp = (unsigned long)except;
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#endif
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#endif
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