URL
https://opencores.org/ocsvn/or1k/or1k/trunk
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 51 |
Rev 64 |
| Line 49... |
Line 49... |
fetch(); /* before starting with exception.*/
|
fetch(); /* before starting with exception.*/
|
decode(&iqueue[0]);
|
decode(&iqueue[0]);
|
execute();
|
execute();
|
}
|
}
|
|
|
/* cont_run = 0; */
|
|
if (!(mfspr(SPR_SR) & SPR_SR_EXR)) {
|
if (!(mfspr(SPR_SR) & SPR_SR_EXR)) {
|
printf("ABORT: Exception occured while exception detection was disabled.\n");
|
printf("ABORT: Exception occured while exception detection was disabled.\n");
|
cont_run = 0;
|
cont_run = 0;
|
return;
|
return;
|
}
|
}
|
|
|
pc_saved = (pc & ~0x3) |
|
pc_saved = pc & ~0x3;
|
(mfspr(SPR_SR) & (SPR_SR_SUPV | SPR_SR_EXR));
|
|
mtspr(SPR_EPCR_BASE, pc_saved);
|
mtspr(SPR_EPCR_BASE, pc_saved);
|
mtspr(SPR_EEAR_BASE, ea);
|
mtspr(SPR_EEAR_BASE, ea);
|
|
mtspr(SPR_ESR_BASE, mfspr(SPR_SR));
|
|
|
|
/* Address translation is always disabled when starting exception. */
|
|
mtspr(SPR_SR, mfspr(SPR_SR) & ~(SPR_SR_DME));
|
|
mtspr(SPR_SR, mfspr(SPR_SR) & ~(SPR_SR_IME));
|
|
|
mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_SUPV); /* SUPV mode */
|
mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_SUPV); /* SUPV mode */
|
mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_EXR); /* Disable except. */
|
mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_EXR); /* Disable except. */
|
pc = (unsigned long)except;
|
pc = (unsigned long)except;
|
pctemp = (unsigned long)except;
|
pctemp = (unsigned long)except;
|
#endif
|
#endif
|
© copyright 1999-2025
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.