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#define SPRGROUP_TT (10<< MAX_SPRS_PER_GRP_BITS)
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#define SPRGROUP_TT (10<< MAX_SPRS_PER_GRP_BITS)
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/* System control and status group */
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/* System control and status group */
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#define SPR_VR (SPRGROUP_SYS + 0)
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#define SPR_VR (SPRGROUP_SYS + 0)
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#define SPR_UPR (SPRGROUP_SYS + 1)
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#define SPR_UPR (SPRGROUP_SYS + 1)
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#define SPR_CPUCFGR (SPRGROUP_SYS + 2)
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#define SPR_DMMUCFGR (SPRGROUP_SYS + 3)
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#define SPR_IMMUCFGR (SPRGROUP_SYS + 4)
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#define SPR_DCCFGR (SPRGROUP_SYS + 5)
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#define SPR_ICCFGR (SPRGROUP_SYS + 6)
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#define SPR_DCFGR (SPRGROUP_SYS + 7)
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#define SPR_PCCFGR (SPRGROUP_SYS + 8)
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#define SPR_PC (SPRGROUP_SYS + 16) /* CZ 21/06/01 */
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#define SPR_PC (SPRGROUP_SYS + 16) /* CZ 21/06/01 */
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#define SPR_SR (SPRGROUP_SYS + 17) /* CZ 21/06/01 */
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#define SPR_SR (SPRGROUP_SYS + 17) /* CZ 21/06/01 */
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#define SPR_EPCR_BASE (SPRGROUP_SYS + 32) /* CZ 21/06/01 */
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#define SPR_EPCR_BASE (SPRGROUP_SYS + 32) /* CZ 21/06/01 */
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#define SPR_EPCR_LAST (SPRGROUP_SYS + 47) /* CZ 21/06/01 */
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#define SPR_EPCR_LAST (SPRGROUP_SYS + 47) /* CZ 21/06/01 */
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#define SPR_EEAR_BASE (SPRGROUP_SYS + 48)
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#define SPR_EEAR_BASE (SPRGROUP_SYS + 48)
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/*
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/*
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* Bit definitions for the Power management register
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* Bit definitions for the Power management register
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*
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*
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*/
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*/
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#define SPR_PMR_SDF 0x00000001 /* Slow down factor */
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#define SPR_PMR_SDF 0x0000000f /* Slow down factor */
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#define SPR_PMR_DME 0x00000002 /* Doze mode enable */
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#define SPR_PMR_DME 0x00000010 /* Doze mode enable */
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#define SPR_PMR_SME 0x00000004 /* Sleep mode enable */
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#define SPR_PMR_SME 0x00000020 /* Sleep mode enable */
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#define SPR_PMR_DCGE 0x00000008 /* Dynamic clock gating enable */
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#define SPR_PMR_DCGE 0x00000040 /* Dynamic clock gating enable */
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#define SPR_PMR_SUME 0x00000010 /* Suspend mode enable */
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#define SPR_PMR_SUME 0x00000080 /* Suspend mode enable */
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/*
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/*
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* Bit definitions for PICMR
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* Bit definitions for PICMR
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*
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*
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*/
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*/
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*/
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*/
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#define SPR_TTCR_PERIOD 0x0fffffff /* Time Period */
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#define SPR_TTCR_PERIOD 0x0fffffff /* Time Period */
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#define SPR_TTMR_PERIOD SPR_TTCR_PERIOD
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#define SPR_TTMR_PERIOD SPR_TTCR_PERIOD
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#define SPR_TTMR_IP 0x10000000 /* Interrupt Pending */
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#define SPR_TTMR_IP 0x10000000 /* Interrupt Pending */
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#define SPR_TTMR_IE 0x20000000 /* Interrupt Enable */
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#define SPR_TTMR_IE 0x20000000 /* Interrupt Enable */
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#define SPR_TTMR_SR 0x40000000 /* Single Run */
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#define SPR_TTMR_RT 0x40000000 /* Restart tick */
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#define SPR_TTMR_TTE 0x80000000 /* Tick Timer Enable */
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#define SPR_TTMR_SR 0x80000000 /* Single run */
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#define SPR_TTMR_M 0xc0000000 /* SR+TTE, Tick Timer Mode */
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#define SPR_TTMR_CR 0xc0000000 /* Continuous run */
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#define SPR_TTMR_M 0xc0000000 /* Tick mode */
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