| Line 60... |
Line 60... |
#define SPR_ESR_BASE (SPRGROUP_SYS + 64)
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#define SPR_ESR_BASE (SPRGROUP_SYS + 64)
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#define SPR_ESR_LAST (SPRGROUP_SYS + 79)
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#define SPR_ESR_LAST (SPRGROUP_SYS + 79)
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/* Data MMU group */
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/* Data MMU group */
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#define SPR_DMMUCR (SPRGROUP_DMMU + 0)
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#define SPR_DMMUCR (SPRGROUP_DMMU + 0)
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#define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x200)
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#define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100)
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#define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x200)
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#define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100)
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#define SPR_DTLBTR_BASE(WAY) (SPRGROUP_DMMU + 0x300 + (WAY) * 0x200)
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#define SPR_DTLBTR_BASE(WAY) (SPRGROUP_DMMU + 0x280 + (WAY) * 0x100)
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#define SPR_DTLBTR_LAST(WAY) (SPRGROUP_DMMU + 0x3ff + (WAY) * 0x200)
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#define SPR_DTLBTR_LAST(WAY) (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x100)
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/* Instruction MMU group */
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/* Instruction MMU group */
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#define SPR_IMMUCR (SPRGROUP_IMMU + 0)
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#define SPR_IMMUCR (SPRGROUP_IMMU + 0)
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#define SPR_ITLBMR_BASE(WAY) (SPRGROUP_IMMU + 0x200 + (WAY) * 0x200)
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#define SPR_ITLBMR_BASE(WAY) (SPRGROUP_IMMU + 0x200 + (WAY) * 0x100)
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#define SPR_ITLBMR_LAST(WAY) (SPRGROUP_IMMU + 0x2ff + (WAY) * 0x200)
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#define SPR_ITLBMR_LAST(WAY) (SPRGROUP_IMMU + 0x27f + (WAY) * 0x100)
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#define SPR_ITLBTR_BASE(WAY) (SPRGROUP_IMMU + 0x300 + (WAY) * 0x200)
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#define SPR_ITLBTR_BASE(WAY) (SPRGROUP_IMMU + 0x280 + (WAY) * 0x100)
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#define SPR_ITLBTR_LAST(WAY) (SPRGROUP_IMMU + 0x3ff + (WAY) * 0x200)
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#define SPR_ITLBTR_LAST(WAY) (SPRGROUP_IMMU + 0x2ff + (WAY) * 0x100)
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/* Data cache group */
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/* Data cache group */
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#define SPR_DCCR (SPRGROUP_DC + 0)
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#define SPR_DCCR (SPRGROUP_DC + 0)
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#define SPR_DCBPR (SPRGROUP_DC + 1)
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#define SPR_DCBPR (SPRGROUP_DC + 1)
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#define SPR_DCBFR (SPRGROUP_DC + 2)
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#define SPR_DCBFR (SPRGROUP_DC + 2)
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| Line 156... |
Line 156... |
/*
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/*
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* Bit definitions for the Supervision Register
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* Bit definitions for the Supervision Register
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*
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*
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*/
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*/
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#define SPR_SR_CID 0xf0000000 /* Context ID */
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#define SPR_SR_CID 0xf0000000 /* Context ID */
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#define SPR_SR_SUMRA 0x00010000 /* Supervisor SPR read access */
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#define SPR_SR_FO 0x00008000 /* Fixed one */
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#define SPR_SR_FO 0x00008000 /* Fixed one */
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#define SPR_SR_EPH 0x00004000 /* Exception Prefixi High */
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#define SPR_SR_EPH 0x00004000 /* Exception Prefix High */
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#define SPR_SR_DSX 0x00002000 /* Delay Slot Exception */
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#define SPR_SR_DSX 0x00002000 /* Delay Slot Exception */
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#define SPR_SR_OVE 0x00001000 /* Overflow flag Exception */
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#define SPR_SR_OVE 0x00001000 /* Overflow flag Exception */
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#define SPR_SR_OV 0x00000800 /* Overflow flag */
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#define SPR_SR_OV 0x00000800 /* Overflow flag */
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#define SPR_SR_CY 0x00000400 /* Carry flag */
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#define SPR_SR_CY 0x00000400 /* Carry flag */
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#define SPR_SR_F 0x00000200 /* Condition Flag */
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#define SPR_SR_F 0x00000200 /* Condition Flag */
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