| Line 103... |
Line 103... |
break;
|
break;
|
default:
|
default:
|
/* Mask reseved bits in DTLBMR and DTLBMR registers */
|
/* Mask reseved bits in DTLBMR and DTLBMR registers */
|
if ( (regno >= SPR_DTLBMR_BASE(0)) && (regno < SPR_DTLBTR_LAST(3))) {
|
if ( (regno >= SPR_DTLBMR_BASE(0)) && (regno < SPR_DTLBTR_LAST(3))) {
|
if((regno & 0xff) < 0x80)
|
if((regno & 0xff) < 0x80)
|
sprs[regno] = ((value / (config.dmmu.pagesize * config.dmmu.nsets)) *
|
sprs[regno] = ((value / config.dmmu.pagesize) * config.dmmu.pagesize) |
|
config.dmmu.pagesize * config.dmmu.nsets) |
|
|
(value & (SPR_DTLBMR_V | SPR_DTLBMR_PL1 | SPR_DTLBMR_CID | SPR_DTLBMR_LRU));
|
(value & (SPR_DTLBMR_V | SPR_DTLBMR_PL1 | SPR_DTLBMR_CID | SPR_DTLBMR_LRU));
|
else
|
else
|
sprs[regno] = ((value / config.dmmu.pagesize) * config.dmmu.pagesize) |
|
sprs[regno] = ((value / config.dmmu.pagesize) * config.dmmu.pagesize) |
|
(value & (SPR_DTLBTR_CC | SPR_DTLBTR_CI | SPR_DTLBTR_WBC | SPR_DTLBTR_WOM |
|
(value & (SPR_DTLBTR_CC | SPR_DTLBTR_CI | SPR_DTLBTR_WBC | SPR_DTLBTR_WOM |
|
SPR_DTLBTR_A | SPR_DTLBTR_D | SPR_DTLBTR_URE | SPR_DTLBTR_UWE | SPR_DTLBTR_SRE |
|
SPR_DTLBTR_A | SPR_DTLBTR_D | SPR_DTLBTR_URE | SPR_DTLBTR_UWE | SPR_DTLBTR_SRE |
|
| Line 116... |
Line 115... |
}
|
}
|
|
|
/* Mask reseved bits in ITLBMR and ITLBMR registers */
|
/* Mask reseved bits in ITLBMR and ITLBMR registers */
|
if ( (regno >= SPR_ITLBMR_BASE(0)) && (regno < SPR_ITLBTR_LAST(3))) {
|
if ( (regno >= SPR_ITLBMR_BASE(0)) && (regno < SPR_ITLBTR_LAST(3))) {
|
if((regno & 0xff) < 0x80)
|
if((regno & 0xff) < 0x80)
|
sprs[regno] = ((value / (config.immu.pagesize * config.immu.nsets)) *
|
sprs[regno] = ((value / config.immu.pagesize) * config.immu.pagesize) |
|
config.immu.pagesize * config.immu.nsets) |
|
|
(value & (SPR_ITLBMR_V | SPR_ITLBMR_PL1 | SPR_ITLBMR_CID | SPR_ITLBMR_LRU));
|
(value & (SPR_ITLBMR_V | SPR_ITLBMR_PL1 | SPR_ITLBMR_CID | SPR_ITLBMR_LRU));
|
else
|
else
|
sprs[regno] = ((value / config.immu.pagesize) * config.immu.pagesize) |
|
sprs[regno] = ((value / config.immu.pagesize) * config.immu.pagesize) |
|
(value & (SPR_ITLBTR_CC | SPR_ITLBTR_CI | SPR_ITLBTR_WBC | SPR_ITLBTR_WOM |
|
(value & (SPR_ITLBTR_CC | SPR_ITLBTR_CI | SPR_ITLBTR_WBC | SPR_ITLBTR_WOM |
|
SPR_ITLBTR_A | SPR_ITLBTR_D | SPR_ITLBTR_SXE | SPR_ITLBTR_UXE));
|
SPR_ITLBTR_A | SPR_ITLBTR_D | SPR_ITLBTR_SXE | SPR_ITLBTR_UXE));
|
