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void mtspr(int regno, sprword value);

sprword mfspr(int regno);

void setsprbit(int regno, int bitnum, unsigned long bitvalue);

int getsprbit(int regno, int bitnum);

void sprs_status();

#define MAX_GRPS 32

#define MAX_SPRS_PER_GRP 0x1000

#define MAX_SPRS (MAX_GRPS * 0x1000000 / MAX_SPRS_PER_GRP)

/* Base addresses for the groups */

#define SPRGROUP_SYS    0x00000000

#define SPRGROUP_DMMU   0x01000000

#define SPRGROUP_IMMU   0x02000000

#define SPRGROUP_DC     0x03000000

#define SPRGROUP_IC     0x04000000

#define SPRGROUP_MAC    0x05000000

/* System control and status group */

#define SPR_VR          (SPRGROUP_SYS + 0)

#define SPR_MPR         (SPRGROUP_SYS + 1)

#define SPR_SR          (SPRGROUP_SYS + 2)

#define SPR_EPCR_BASE   (SPRGROUP_SYS + 16)

#define SPR_EPCR_LAST   (SPRGROUP_SYS + 31)

#define SPR_CTR_BASE    (SPRGROUP_SYS + 32)

#define SPR_CTR_LAST    (SPRGROUP_SYS + 47)

#define SPR_EEAR_BASE   (SPRGROUP_SYS + 48)

#define SPR_EEAR_LAST   (SPRGROUP_SYS + 63)

/* Data MMU group */

#define SPR_DTLBMR_BASE (SPRGROUP_DMMU + 0)

#define SPR_DTLBMR_LAST (SPRGROUP_DMMU + 255)

#define SPR_DTLBTR_BASE (SPRGROUP_DMMU + 256)

#define SPR_DTLBTR_LAST (SPRGROUP_DMMU + 511)

#define SPR_DMMUCR      (SPRGROUP_DMMU + 512)

/* Instruction MMU group */

#define SPR_ITLBMR_BASE (SPRGROUP_IMMU + 0)

#define SPR_ITLBMR_LAST (SPRGROUP_IMMU + 255)

#define SPR_ITLBTR_BASE (SPRGROUP_IMMU + 256)

#define SPR_ITLBTR_LAST (SPRGROUP_IMMU + 511)

#define SPR_IMMUCR      (SPRGROUP_IMMU + 512)

/* Data cache group */

#define SPR_DCR_BASE    (SPRGROUP_DC + 0)

#define SPR_DCR_LAST    (SPRGROUP_DC + 511)

#define SPR_DCCR        (SPRGROUP_DC + 512)

/* Instruction cache group */

#define SPR_ICR_BASE    (SPRGROUP_IC + 0)

#define SPR_ICR_LAST    (SPRGROUP_IC + 511)

#define SPR_ICCR        (SPRGROUP_IC + 512)

/* MAC group */

#define SPR_MACLO (SPRGROUP_MAC + 1)

#define SPR_MACHI (SPRGROUP_MAC + 2)

/*

 * Bit definitions for the Version Register

 *

 */

#define SPR_VR_VER      0xffff0000  /* Processor version */

#define SPR_VR_PT       0x0000f000  /* Predefined template */

#define SPR_VR_REV      0x0000003f  /* Processor revision */

/*

 * Bit definitions for the Module Present Register

 *

 */

#define SPR_MPR_SYS     0x00000001  /* System control and status module */

#define SPR_MPR_DMMU    0x00000002  /* Data MMU module */

#define SPR_MPR_IMMU    0x00000004  /* Instruction MMU module */

#define SPR_MPR_DC      0x00000008  /* Data cache module */

#define SPR_MPR_IC      0x00000010  /* Instruction cache module */

#define SPR_MPR_MAC     0x00000020  /* MAC module */

#define SPR_MPR_RES     0xffffffc0  /* Custom and future modules */

/*

 * Bit definitions for the Supervision Register

 *

 */

#define SPR_SR_CID      0xf0000000  /* Context ID */

#define SPR_SR_LEE      0x00000080  /* Little Endian Enable */

#define SPR_SR_IME      0x00000040  /* Instruction MMU Enable */

#define SPR_SR_DME      0x00000020  /* Data MMU Enable */

#define SPR_SR_ICE      0x00000010  /* Instruction Cache Enable */

#define SPR_SR_DCE      0x00000008  /* Data Cache Enable */

#define SPR_SR_EIR      0x00000004  /* External Interrupt Recognition */

#define SPR_SR_EXR      0x00000002  /* Exception Recognition */

#define SPR_SR_SUPV     0x00000001  /* Supervisor mode */

/*

 * Bit definitions for the Data MMU Control Register

 *

 */

#define SPR_DMMUCR_P2S  0x0000003e  /* Level 2 Page Size */

#define SPR_DMMUCR_P1S  0x000007c0  /* Level 1 Page Size */

#define SPR_DMMUCR_VADDR_WIDTH  0x0000f800  /* Virtual ADDR Width */

#define SPR_DMMUCR_PADDR_WIDTH  0x000f0000  /* Physical ADDR Width */

/*

 * Bit definitions for the Instruction MMU Control Register

 *

 */

#define SPR_IMMUCR_P2S  0x0000003e  /* Level 2 Page Size */

#define SPR_IMMUCR_P1S  0x000007c0  /* Level 1 Page Size */

#define SPR_IMMUCR_VADDR_WIDTH  0x0000f800  /* Virtual ADDR Width */

#define SPR_IMMUCR_PADDR_WIDTH  0x000f0000  /* Physical ADDR Width */

/*

 * Bit definitions for the Data TLB Match Register

 *

 */

#define SPR_DTLBMR_PL1  0x00000001  /* Page Level 1 (if 0 then PL2)*/

#define SPR_DTLBMR_CID  0x0000001e  /* Context ID */

#define SPR_DTLBMR_VPN  0xfffffc00  /* Virtual Page Number */

/*

 * Bit definitions for the Data TLB Translate Register

 *

 */

#define SPR_DTLBTR_V    0x00000001  /* Valid */

#define SPR_DTLBTR_CC   0x00000002  /* Cache Coherency */

#define SPR_DTLBTR_CI   0x00000004  /* Cache Inhibit */

#define SPR_DTLBTR_WBC  0x00000008  /* Write-Back Cache*/

#define SPR_DTLBTR_WOM  0x00000010  /* Weakly-Ordered Memory */

#define SPR_DTLBTR_A    0x00000020  /* Accessed */

#define SPR_DTLBTR_D    0x00000040  /* Dirty */

#define SPR_DTLBTR_PPI  0x00000380  /* Page Protection Index */

#define SPR_DTLBTR_PPN  0xfffffc00  /* Physical Page Number */

/*

 * Bit definitions for the Instruction TLB Match Register

 *

 */

#define SPR_ITLBMR_PL1  0x00000001  /* Page Level 1 (if 0 then PL2)*/

#define SPR_ITLBMR_CID  0x0000001e  /* Context ID */

#define SPR_ITLBMR_VPN  0xfffffc00  /* Virtual Page Number */

/*

 * Bit definitions for the Instruction TLB Translate Register

 *

 */

#define SPR_ITLBTR_V    0x00000001  /* Valid */

#define SPR_ITLBTR_CC   0x00000002  /* Cache Coherency */

#define SPR_ITLBTR_CI   0x00000004  /* Cache Inhibit */

#define SPR_ITLBTR_WBC  0x00000008  /* Write-Back Cache*/

#define SPR_ITLBTR_WOM  0x00000010  /* Weakly-Ordered Memory */

#define SPR_ITLBTR_A    0x00000020  /* Accessed */

#define SPR_ITLBTR_D    0x00000040  /* Dirty */

#define SPR_ITLBTR_PPI  0x00000380  /* Page Protection Index */

#define SPR_ITLBTR_PPN  0xfffffc00  /* Physical Page Number */