| Line 42... |
Line 42... |
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/* System control and status group */
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/* System control and status group */
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#define SPR_VR (SPRGROUP_SYS + 0)
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#define SPR_VR (SPRGROUP_SYS + 0)
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#define SPR_MPR (SPRGROUP_SYS + 1)
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#define SPR_MPR (SPRGROUP_SYS + 1)
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#define SPR_SR (SPRGROUP_SYS + 2)
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#define SPR_SR (SPRGROUP_SYS + 2)
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#define SPR_CCR (SPRGROUP_SYS + 3)
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#define SPR_EPCR_BASE (SPRGROUP_SYS + 16)
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#define SPR_EPCR_BASE (SPRGROUP_SYS + 16)
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#define SPR_EPCR_LAST (SPRGROUP_SYS + 31)
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#define SPR_EPCR_LAST (SPRGROUP_SYS + 31)
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#define SPR_CTR_BASE (SPRGROUP_SYS + 32)
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#define SPR_CTR_BASE (SPRGROUP_SYS + 32)
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#define SPR_CTR_LAST (SPRGROUP_SYS + 47)
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#define SPR_CTR_LAST (SPRGROUP_SYS + 47)
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#define SPR_EEAR_BASE (SPRGROUP_SYS + 48)
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#define SPR_EEAR_BASE (SPRGROUP_SYS + 48)
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| Line 112... |
Line 113... |
#define SPR_SR_EIR 0x00000004 /* External Interrupt Recognition */
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#define SPR_SR_EIR 0x00000004 /* External Interrupt Recognition */
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#define SPR_SR_EXR 0x00000002 /* Exception Recognition */
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#define SPR_SR_EXR 0x00000002 /* Exception Recognition */
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#define SPR_SR_SUPV 0x00000001 /* Supervisor mode */
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#define SPR_SR_SUPV 0x00000001 /* Supervisor mode */
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/*
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/*
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* Bit definitions for the Condition Code Register
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*
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*/
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#define SPR_CCR_OVERFL 0x00000004 /* Overflow */
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#define SPR_CCR_CARRY 0x00000002 /* Carry */
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#define SPR_CCR_FLAG 0x00000001 /* Compare Flag */
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/*
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* Bit definitions for the Data MMU Control Register
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* Bit definitions for the Data MMU Control Register
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*
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*
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*/
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*/
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#define SPR_DMMUCR_P2S 0x0000003e /* Level 2 Page Size */
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#define SPR_DMMUCR_P2S 0x0000003e /* Level 2 Page Size */
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#define SPR_DMMUCR_P1S 0x000007c0 /* Level 1 Page Size */
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#define SPR_DMMUCR_P1S 0x000007c0 /* Level 1 Page Size */
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