| Line 90... |
Line 90... |
{
|
{
|
unsigned long op = f->INSN(ref).op[j];
|
unsigned long op = f->INSN(ref).op[j];
|
unsigned long opt = f->INSN(ref).opt[j];
|
unsigned long opt = f->INSN(ref).opt[j];
|
switch (opt & ~OPT_DEST) {
|
switch (opt & ~OPT_DEST) {
|
case OPT_NONE: assert (0); break;
|
case OPT_NONE: assert (0); break;
|
case OPT_CONST: if (f->INSN(ref).type & IT_COND) {
|
case OPT_CONST: if (f->INSN(ref).type & IT_COND && f->INSN(ref).insn == II_CMOV) {
|
assert (op == 0 || op == 1);
|
assert (op == 0 || op == 1);
|
sprintf (s, "1'b%x", op);
|
sprintf (s, "1'b%x", op);
|
} else sprintf (s, "32'h%x", op);
|
} else sprintf (s, "32'h%x", op);
|
break;
|
break;
|
case OPT_REGISTER:
|
case OPT_REGISTER:
|
| Line 315... |
Line 315... |
if (f->nfdeps) {
|
if (f->nfdeps) {
|
GEN ("\n/* Function calls */\n");
|
GEN ("\n/* Function calls */\n");
|
GEN ("output [31:0] fr3_o");
|
GEN ("output [31:0] fr3_o");
|
for (i = 1; i < 6; i++) GEN (", fr%i_o", i + 3);
|
for (i = 1; i < 6; i++) GEN (", fr%i_o", i + 3);
|
GEN (";\n");
|
GEN (";\n");
|
|
GEN ("input [31:0] fr11_i;\n");
|
if (log2(f->nfdeps) > 0) GEN ("output [%i:0] fid_o;\n", log2(f->nfdeps));
|
if (log2(f->nfdeps) > 0) GEN ("output [%i:0] fid_o;\n", log2(f->nfdeps));
|
GEN ("output fstart_o;\n");
|
GEN ("output fstart_o;\n");
|
GEN ("input fend_i;\n");
|
GEN ("input fend_i;\n");
|
}
|
}
|
|
|
| Line 454... |
Line 455... |
GEN ("wire end_o = bb_stb[%i]", end_bb_no);
|
GEN ("wire end_o = bb_stb[%i]", end_bb_no);
|
if (end_bb->mdep) {
|
if (end_bb->mdep) {
|
GEN (" && ");
|
GEN (" && ");
|
print_deps (fo, f, end_bb_no, end_bb->mdep, 0);
|
print_deps (fo, f, end_bb_no, end_bb->mdep, 0);
|
}
|
}
|
GEN ("wire busy_o = |bb_stb\n");
|
|
|
|
/* Is there a loop right at end? */
|
/* Is there a loop right at end? */
|
if (end_bb->next[0] >= 0) {
|
if (end_bb->next[0] >= 0) {
|
int bidx = branch_index (end_bb);
|
int bidx = branch_index (end_bb);
|
char t[30];
|
char t[30];
|
print_op_v (f, t, REF (end_bb_no, bidx), 1);
|
print_op_v (f, t, REF (end_bb_no, bidx), 1);
|
GEN (" && !%s", t);
|
GEN (" && !%s", t);
|
}
|
}
|
GEN (";\n");
|
GEN (";\n");
|
|
GEN ("wire busy_o = |bb_stb;\n");
|
|
|
|
|
GEN ("\n/* Basic block triggers */\n");
|
GEN ("\n/* Basic block triggers */\n");
|
GEN ("wire [%2i:0] bb_start = {\n", f->num_bb - 1);
|
GEN ("wire [%2i:0] bb_start = {\n", f->num_bb - 1);
|
for (b = f->num_bb - 1; b >= 0; b--) {
|
for (b = f->num_bb - 1; b >= 0; b--) {
|
GEN (" /* bb_start[%2i] */ ", b);
|
GEN (" /* bb_start[%2i] */ ", b);
|
| Line 479... |
Line 481... |
print_deps (fo, f, f->bb[b].prev[0], prev->mdep, 0);
|
print_deps (fo, f, f->bb[b].prev[0], prev->mdep, 0);
|
GEN (" && ");
|
GEN (" && ");
|
}
|
}
|
GEN ("bb_stb[%i]", f->bb[b].prev[0]);
|
GEN ("bb_stb[%i]", f->bb[b].prev[0]);
|
if (prev->next[0] >= 0 && prev->next[1] >= 0) {
|
if (prev->next[0] >= 0 && prev->next[1] >= 0) {
|
int bidx = branch_index (&f->bb[f->bb[b].prev[0]]);
|
int bi = REF (f->bb[b].prev[0], branch_index (&f->bb[f->bb[b].prev[0]]));
|
assert (bidx >= 0);
|
int ci;
|
GEN (" && ");
|
assert (bi >= 0);
|
|
ci = f->INSN(bi).op[1];
|
t = prev->next[0] == b;
|
t = prev->next[0] == b;
|
GEN ("%st%x_%x", t ? "" : "!", f->bb[b].prev[0], bidx);
|
GEN (" && ");
|
|
if (f->INSN(bi).opt[1] & OPT_REF) {
|
|
GEN ("%st%x_%x", t ? "" : "!", REF_BB(ci), REF_I(ci));
|
|
} else {
|
|
fprintf (stderr, "%x!%x!%x\n", bi, ci, f->INSN(bi).opt[1]);
|
|
assert (f->INSN(bi).opt[1] & OPT_CONST);
|
|
GEN ("%s%i", t ? "" : "!", ci);
|
|
}
|
}
|
}
|
if (f->bb[b].prev[1] >= 0) {
|
if (f->bb[b].prev[1] >= 0) {
|
prev = &f->bb[f->bb[b].prev[1]];
|
prev = &f->bb[f->bb[b].prev[1]];
|
GEN ("\n || ");
|
GEN ("\n || ");
|
if (prev->mdep) {
|
if (prev->mdep) {
|
| Line 693... |
Line 703... |
GEN ("always @(posedge clk or posedge rst)\n");
|
GEN ("always @(posedge clk or posedge rst)\n");
|
GEN ("begin\n");
|
GEN ("begin\n");
|
GEN (" if (rst) bb_stb <= #Tp %i'h%x;\n", f->num_bb, 0);
|
GEN (" if (rst) bb_stb <= #Tp %i'h%x;\n", f->num_bb, 0);
|
GEN (" else if (end_o) bb_stb <= #Tp %i'h%x;\n", f->num_bb, 0);
|
GEN (" else if (end_o) bb_stb <= #Tp %i'h%x;\n", f->num_bb, 0);
|
for (i = 0; i < f->num_bb; i++) {
|
for (i = 0; i < f->num_bb; i++) {
|
GEN (" else if (bb_start[%i]) begin\n", i);
|
GEN (" end else if (bb_start[%i]) begin\n", i);
|
GEN (" bb_stb <= #Tp %i'h%x;\n", f->num_bb, 1 << i);
|
GEN (" bb_stb <= #Tp %i'h%x;\n", f->num_bb, 1 << i);
|
}
|
}
|
GEN (" end else if (end_o) begin\n");
|
GEN (" end else if (end_o) begin\n");
|
GEN (" bb_stb <= #Tp %i'h%x;\n", f->num_bb, 0);
|
GEN (" bb_stb <= #Tp %i'h%x;\n", f->num_bb, 0);
|
GEN (" end\n");
|
GEN (" end\n");
|
| Line 766... |
Line 776... |
GEN ("output [3:0] lwb_sel_o, swb_sel_o;\n");
|
GEN ("output [3:0] lwb_sel_o, swb_sel_o;\n");
|
GEN ("output [31:0] lwb_adr_o, swb_adr_o, swb_dat_o, cuc_dat_o;\n");
|
GEN ("output [31:0] lwb_adr_o, swb_adr_o, swb_dat_o, cuc_dat_o;\n");
|
GEN ("input [15:0] cuc_adr_i;\n");
|
GEN ("input [15:0] cuc_adr_i;\n");
|
GEN ("input [31:0] lwb_dat_i, cuc_dat_i;\n\n");
|
GEN ("input [31:0] lwb_dat_i, cuc_dat_i;\n\n");
|
|
|
/* Function specific data */
|
GEN ("wire [%2i:0] i_we, i_re, i_start, i_finish, i_selected, i_first_reg;\n", nrf - 1);
|
for (i = 0; i < nfuncs; i++) if (f[i]) {
|
GEN ("wire [%2i:0] i_bidok, main_start, main_end;\n", nrf - 1);
|
int ci = 0, co = 0;
|
GEN ("reg [%2i:0] i_go_bsy, main_start_r;\n", nrf - 1);
|
int fn = f[i]->tmp;
|
|
GEN ("\n/* Registers for function %s */\n", prof_func[i].name);
|
|
GEN ("wire i%i_we = cuc_stb_i && cuc_we_i && cuc_adr_i[15:6] == %i;\n", fn, fn);
|
|
GEN ("wire i%i_re = cuc_stb_i && !cuc_we_i && cuc_adr_i[15:6] == %i;\n", fn, fn);
|
|
GEN ("wire i%i_start, i%i_finish;\n\n", fn, fn);
|
|
|
|
GEN ("assign i%i_start = i%i_go_bsy & cuc_ack_o;\n", fn, fn);
|
|
GEN ("wire main_start%i = start_i && cuc_adr_i[15:6] == %i && cuc_adr_i[5:0] == %i && i%i_we;\n",
|
|
i, i, j, i);
|
|
GEN ("wire main_end%i = end_i && cuc_adr_i[15:6] == %i && cuc_adr_i[5:0] == %i && i%i_we;\n",
|
|
i, i, j, i);
|
|
|
|
GEN ("\nalways @(posedge clk or posedge rst)\n");
|
GEN ("assign i_selected = {\n");
|
GEN (" begin\n");
|
for (i = 0; i < nrf; i++)
|
GEN (" if (rst) cuc_ack_o <= #Tp 1'b0;\n");
|
GEN (" cuc_adr_i[15:6] == %i%s\n", i, i < nrf - 1 ? "," : "};");
|
GEN (" else if ((i%i_we | i%i_re) & !i%i_go_bsy)\n", fn, fn, fn);
|
|
GEN (" cuc_ack_o <= #Tp ~cuc_ack_o;\n");
|
GEN ("assign i_first_reg = {\n");
|
GEN (" end\n");
|
for (i = 0; i < nrf; i++) {
|
|
for (j = 0; j <= MAX_REGS; j++) if (f[i]->used_regs[j]) break;
|
|
GEN (" cuc_adr_i[5:0] == %i%s\n", j, i < nrf - 1 ? "," : "};");
|
|
}
|
|
|
|
GEN ("assign i_we = {%i{cuc_stb_i && cuc_we_i}} & i_selected;\n", nrf);
|
|
GEN ("assign i_re = {%i{cuc_stb_i && !cuc_we_i}} & i_selected;\n", nrf);
|
|
|
|
GEN ("assign i_start = i_go_bsy & {%i{cuc_ack_o}};\n", nrf);
|
|
GEN ("assign i_start_bidok = {\n");
|
|
for (i = 0; i < nrf; i++)
|
|
GEN (" i_start_bid[%i] < %i%s\n", i, i, i < nrf - 1 ? "," : "};");
|
|
GEN ("assign main_start = start_i & i_selected & i_first_reg & i_we;\n");
|
|
GEN ("assign main_end = {%i{end_i}} & i_selected;\n");
|
|
|
GEN ("\nalways @(posedge clk or posedge rst)\n");
|
GEN ("\nalways @(posedge clk or posedge rst)\n");
|
GEN ("begin\n");
|
GEN ("begin\n");
|
GEN (" if (rst) i%i_go_bsy <= #Tp 1'b0;\n", fn);
|
GEN (" if (rst) i_go_bsy <= #Tp %i'b0;\n", nrf);
|
GEN (" else if (i%i_we && (cuc_adr_i[15:6] == %i)) i%i_go_bsy <= #Tp 1'b1;\n", fn, fn, fn);
|
GEN (" else i_go_bsy <= #Tp i_we | ~i_finish & i_go_bsy;\n");
|
GEN (" else if (i%i_finish) i%i_go_bsy <= #Tp 1'b0;\n", fn, fn);
|
|
GEN ("end\n");
|
GEN ("end\n");
|
|
|
|
/* Function specific data */
|
|
for (i = 0; i < nfuncs; i++) if (f[i]) {
|
|
int ci = 0, co = 0;
|
|
int fn = f[i]->tmp;
|
|
GEN ("\n/* Registers for function %s */\n", prof_func[i].name);
|
for (j = 0, first = 1; j < MAX_REGS; j++) if (f[i]->used_regs[j]) {
|
for (j = 0, first = 1; j < MAX_REGS; j++) if (f[i]->used_regs[j]) {
|
GEN ("%s i%i_r%ii", first ? "\n/* inputs */\nreg [31:0]" : ",", fn, j);
|
GEN ("%s i%i_r%ii", first ? "/* inputs */\nreg [31:0]" : ",", fn, j);
|
first = 0;
|
first = 0;
|
ci++;
|
ci++;
|
}
|
}
|
if (ci) GEN (";\n");
|
if (ci) GEN (";\n");
|
|
|
for (j = 0, first = 1; j < MAX_REGS; j++)
|
for (j = 0, first = 1; j < MAX_REGS; j++)
|
if (f[i]->lur[j] >= 0 && !f[i]->saved_regs[j]) {
|
if (f[i]->lur[j] >= 0 && !f[i]->saved_regs[j]) {
|
GEN ("%s i%i_r%io", first ? "\n/* outputs */\nreg [31:0]" : ",", fn, j);
|
GEN ("%s i%i_r%io", first ? "/* outputs */\nreg [31:0]" : ",", fn, j);
|
first = 0;
|
first = 0;
|
co++;
|
co++;
|
}
|
}
|
if (co) GEN (";\n");
|
if (co) GEN (";\n");
|
|
|
//GEN ("wire [31:0] i%i_r11;\n\n");
|
GEN ("always @(posedge clk or posedge rst)\n");
|
|
GEN (" if (rst) main_start_r <= #Tp %i'b0;\n", nrf);
|
|
GEN (" else main_start_r <= #Tp main_start & i_start_bidok | i_busy | ~i_end & main_start_r;\n");
|
|
|
if (ci) {
|
if (ci) {
|
GEN ("\n/* write register access */\n");
|
GEN ("\n/* write register access */\n");
|
GEN ("always @(posedge clk or posedge rst)\n");
|
GEN ("always @(posedge clk or posedge rst)\n");
|
GEN ("begin\n");
|
GEN ("begin\n");
|
GEN (" if (rst) begin\n");
|
GEN (" if (rst) begin\n");
|
for (j = 0; j < MAX_REGS; j++) if (f[i]->used_regs[j])
|
for (j = 0; j < MAX_REGS; j++) if (f[i]->used_regs[j])
|
GEN (" i%i_r%-2i <= #Tp 32'h0;\n", fn, j);
|
GEN (" i%i_r%-2i <= #Tp 32'h0;\n", fn, j);
|
GEN (" end else if (!i%i_go_bsy && i%i_we)\n", fn, fn);
|
GEN (" end else if (!i_go_bsy[%i] && i_we[%i])\n", fn, fn);
|
GEN (" case (cuc_adr_i[5:0])\n");
|
GEN (" case (cuc_adr_i[5:0])\n");
|
for (j = 0; j < MAX_REGS; j++) if (f[i]->used_regs[j])
|
for (j = 0; j < MAX_REGS; j++) if (f[i]->used_regs[j])
|
GEN (" %-2i: r%i <= #Tp cuc_dat_i;\n", j, j);
|
GEN (" %-2i: r%i <= #Tp cuc_dat_i;\n", j, j);
|
GEN (" endcase\n");
|
GEN (" endcase\n");
|
GEN ("end\n");
|
GEN ("end\n");
|
}
|
}
|
|
|
GEN ("\n\n");
|
GEN ("\n");
|
}
|
}
|
|
|
/* Generate machine for reading all function registers. First registers can delay
|
/* Generate machine for reading all function registers. Register read can be
|
transfer till function completion */
|
delayed till function completion */
|
{
|
{
|
int co;
|
int co;
|
GEN ("/* read register access - data */\n");
|
GEN ("/* read register access - data */\n");
|
GEN ("always @(posedge clk or posedge rst)\n");
|
GEN ("always @(posedge clk or posedge rst)\n");
|
GEN (" if (rst) cuc_dat_o <= #Tp 32'h0;\n");
|
GEN (" if (rst) cuc_dat_o <= #Tp 32'h0;\n");
|
| Line 845... |
Line 863... |
for (i = 0; i < nfuncs; i++) if (f[i]) {
|
for (i = 0; i < nfuncs; i++) if (f[i]) {
|
co = 0;
|
co = 0;
|
for (j = 0; j < MAX_REGS; j++)
|
for (j = 0; j < MAX_REGS; j++)
|
if (f[i]->lur[j] >= 0 && !f[i]->saved_regs[j]) co++;
|
if (f[i]->lur[j] >= 0 && !f[i]->saved_regs[j]) co++;
|
|
|
GEN ("if (cuc_addr_i[15:6] == %i) begin\n", f[i]->tmp);
|
GEN ("if (cuc_addr_i[15:6] == %i)", f[i]->tmp);
|
if (co) {
|
if (co) {
|
first = 1;
|
first = 1;
|
GEN (" case (cuc_adr_i[5:0])\n");
|
GEN ("\n case (cuc_adr_i[5:0])\n");
|
for (j = 0; j < MAX_REGS; j++)
|
for (j = 0; j < MAX_REGS; j++)
|
if (f[i]->lur[j] >= 0 && !f[i]->saved_regs[j])
|
if (f[i]->lur[j] >= 0 && !f[i]->saved_regs[j])
|
GEN (" %-2i: cuc_dat_o <= #Tp i%i_r%i;\n", j, f[i]->tmp, j);
|
GEN (" %-2i: cuc_dat_o <= #Tp i%i_r%i;\n", j, f[i]->tmp, j);
|
GEN (" endcase\n");
|
GEN (" endcase\n");
|
} else {
|
} else {
|
/* no registers => just write an acknowledge */
|
|
GEN (" cuc_dat_o <= #Tp 32'hx;\n");
|
GEN (" cuc_dat_o <= #Tp 32'hx;\n");
|
}
|
}
|
GEN (" end else ");
|
GEN (" else ");
|
}
|
}
|
GEN ("cuc_dat_o <= #Tp 32'hx;\n");
|
GEN ("cuc_dat_o <= #Tp 32'hx;\n");
|
GEN (" else cuc_dat_o <= #Tp 32'hx;\n");
|
GEN (" else cuc_dat_o <= #Tp 32'hx;\n");
|
GEN ("end\n");
|
GEN ("end\n");
|
|
|
GEN ("\n/* read register access - acknowledge */\n");
|
GEN ("\n/* read register access - acknowledge */\n");
|
GEN ("always @(cuc_stb_i or cuc_we_i or cuc_adr_i");
|
GEN ("always @(cuc_stb_i or cuc_we_i or cuc_adr_i");
|
for (i = 0; i < nrf; i++) GEN (" or main_end%i", i);
|
for (i = 0; i < nrf; i++) GEN (" or main_end%i", i);
|
GEN (")\n");
|
GEN (")\n");
|
GEN (" if (cuc_stb_i && cuc_we_i) begin\n");
|
GEN (" if (cuc_stb_i && cuc_we_i) cuc_ack_o <= #Tp |(i_selected & main_end)\n");
|
GEN (" ");
|
|
|
|
for (i = 0; i < nfuncs; i++) if (f[i]) {
|
|
GEN (" if (cuc_addr_i[15:6] == %i) cuc_ack_o <= #Tp main_end%i;\n",
|
|
f[i]->tmp, f[i]->tmp);
|
|
GEN (" else ");
|
|
}
|
|
GEN ("cuc_ack_o <= #Tp 1'b0;\n");
|
|
GEN (" else cuc_ack_o <= #Tp 1'b0;\n");
|
GEN (" else cuc_ack_o <= #Tp 1'b0;\n");
|
GEN ("end\n");
|
GEN ("end\n");
|
}
|
}
|
|
|
for (j = 0; j < 2; j++) {
|
for (j = 0; j < 2; j++) {
|
char t = j ? 's' : 'l';
|
char t = j ? 's' : 'l';
|
GEN ("\n/* %s Wishbone bridge */\n", j ? "store" : "load");
|
GEN ("\n/* %s Wishbone bridge */\n", j ? "store" : "load");
|
GEN ("reg [%2i:0] %cm_sel;\n", log2 (nrf), t);
|
GEN ("reg [%i:0] %cm_sel;\n", log2 (nrf), t);
|
GEN ("reg [%2i:0] %cm_bid;\n", log2 (nrf), t);
|
GEN ("reg [%i:0] %cm_bid;\n", log2 (nrf), t);
|
|
|
GEN ("\n/* highest bid */\n");
|
GEN ("\n/* highest bid */\n");
|
GEN ("always @(");
|
GEN ("always @(");
|
for (i = 0; i < nrf; i++) GEN ("%si%i_%cwb_cycstb", i > 0 ? " or " : "", i, t);
|
for (i = 0; i < nrf; i++) GEN ("%si%i_%cwb_cycstb", i > 0 ? " or " : "", i, t);
|
GEN (")\n");
|
GEN (")\n");
|
| Line 954... |
Line 963... |
GEN ("i%i_lwb_linbrst;\n", nrf - 1);
|
GEN ("i%i_lwb_linbrst;\n", nrf - 1);
|
|
|
/* start/end signals */
|
/* start/end signals */
|
GEN ("\n\n/* start/end signals */\n");
|
GEN ("\n\n/* start/end signals */\n");
|
|
|
|
for (i = 0; i < nrf; i++) {
|
|
if (log2 (maxncallees + 1))
|
|
GEN ("wire [%i:0] i%i_current = i%i_busy ? i%i_current_r : i%i_start_bid;\n",
|
|
log2 (maxncallees + 1), i, i, i, i, i);
|
|
else GEN ("wire i%i_current = 0;\n", i);
|
|
}
|
|
GEN ("\n");
|
|
|
for (i = 0, first = 1; i < nrf; i++) {
|
for (i = 0, first = 1; i < nrf; i++) {
|
GEN ("%si%i_current == %i && i%i_end", first ? "assign end_o = " : "\n || ", i, i, i);
|
GEN ("%si%i_current == %i && i_end[%i]", first ? "assign end_o = " : "\n || ", i, ncallees[i], i);
|
first = 0;
|
first = 0;
|
}
|
}
|
GEN (";\n\n");
|
GEN (";\n\n");
|
|
|
for (i = 0, j = 0; i < nfuncs; i++) if (f[i]) {
|
for (i = 0, j = 0; i < nfuncs; i++) if (f[i]) {
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| Line 971... |
Line 988... |
GEN (")\n");
|
GEN (")\n");
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GEN ("begin !!!\n"); //TODO
|
GEN ("begin !!!\n"); //TODO
|
GEN (" \n");
|
GEN (" \n");
|
GEN ("end\n");
|
GEN ("end\n");
|
}
|
}
|
GEN ("wire i%i_start = start_i;\n", j);
|
GEN ("wire i%i_start = main_start[%i];\n", j, j);
|
j++;
|
j++;
|
}
|
}
|
GEN ("\n");
|
GEN ("\n");
|
|
|
for (i = 0, first = 1; i < nrf; i++) {
|
|
if (log2 (maxncallees + 1))
|
|
GEN ("wire [%i:0] i%i_current = i%i_busy ? i%i_current_r : i%i_start_bid;\n",
|
|
log2 (maxncallees + 1), i, i, i, i, i);
|
|
else GEN ("wire i%i_current = 0;\n", i);
|
|
}
|
|
GEN ("\n");
|
|
|
|
for (i = 0, first = 1; i < nrf; i++) {
|
|
int rf;
|
|
/* Find real function */
|
|
for (rf = 0; rf < nfuncs; rf++) if (f[rf]->tmp == i) break;
|
|
|
|
/* Find first register, use r31, if none */
|
|
for (j = 0; j < MAX_REGS; j++) if (f[rf]->used_regs[j]) break;
|
|
GEN ("/* Function %s */\n", prof_func[rf].name);
|
|
GEN ("reg main_start%i_r;\n", i);
|
|
GEN ("always @(posedge clk or posedge rst)\n");
|
|
GEN (" if (rst) main_start%i_r <= #Tp 1'b0;\n", i);
|
|
GEN (" else if (main_start%i && (i%i_start_bid < %i || i%i_busy))",
|
|
i, i, i, ncallees[i], i);
|
|
GEN (" main_start%i_r <= #Tp 1'b1;\n", i);
|
|
GEN (" else if (main_end%i && i%i_re) main_start%i_r <= #Tp 1'b0;\n", i, i, i);
|
|
}
|
|
|
|
for (i = 0; i < nfuncs; i++) if (f[i]) {
|
for (i = 0; i < nfuncs; i++) if (f[i]) {
|
int nf = f[i]->tmp;
|
int nf = f[i]->tmp;
|
GEN ("\n%s i%i(.clk(clk), .rst(rst),\n", prof_func[i].name, nf);
|
GEN ("\n%s i%i(.clk(clk), .rst(rst),\n", prof_func[i].name, nf);
|
GEN ("");
|
GEN ("");
|
GEN (" .lwb_adr_o(i%i_lwb_adr), .lwb_dat_i(i%i_lwb_dat), .lwb_cycstb_o(i%i_lwb_cycstb),\n",
|
GEN (" .lwb_adr_o(i%i_lwb_adr), .lwb_dat_i(i%i_lwb_dat), .lwb_cycstb_o(i%i_lwb_cycstb),\n",
|
| Line 1014... |
Line 1006... |
GEN (" .swb_adr_o(i%i_swb_adr), .swb_dat_o(i%i_swb_dat), .swb_cycstb_o(i%i_swb_cycstb),\n",
|
GEN (" .swb_adr_o(i%i_swb_adr), .swb_dat_o(i%i_swb_dat), .swb_cycstb_o(i%i_swb_cycstb),\n",
|
nf, nf, nf);
|
nf, nf, nf);
|
GEN (" .swb_sel_o(i%i_swb_sel), .swb_linbrst_o(i%i_swb_linbrst), .swb_ack_i(i%i_swb_ack),\n",
|
GEN (" .swb_sel_o(i%i_swb_sel), .swb_linbrst_o(i%i_swb_linbrst), .swb_ack_i(i%i_swb_ack),\n",
|
nf, nf, nf);
|
nf, nf, nf);
|
GEN (" ");
|
GEN (" ");
|
for (j = 0; j < MAX_REGS; j++) if (f[i]->used_regs[j])
|
for (j = 0, first = 1; j < MAX_REGS; j++) if (f[i]->used_regs[j])
|
GEN (".r%i_i(i%i_r%ii), ", j, nf, j);
|
GEN (".r%i_i(i_r%ii[%i]), ", j, j, nf), first = 0;
|
|
|
GEN ("\n ");
|
if (first) GEN ("\n ");
|
for (j = 0, first = 1; j < MAX_REGS; j++)
|
for (j = 0, first = 1; j < MAX_REGS; j++)
|
if (f[i]->lur[j] >= 0 && !f[i]->saved_regs[j])
|
if (f[i]->lur[j] >= 0 && !f[i]->saved_regs[j])
|
GEN (".r%i_o(i%i_r%io), ", j, nf, j);
|
GEN (".r%i_o(i_r%io[%i]), ", j, j, nf), first = 0;
|
GEN ("\n .start_i(i%i_start), .end_o(i%i_end));\n", nf, nf);
|
if (first) GEN ("\n ");
|
|
if (f[i]->nfdeps) {
|
|
GEN (".fstart_o(i_fstart[%i]), .fend_i(i_fend[%i]), .fid_o(i%i_fid),\n", i, i, i),
|
|
GEN (" .fr3_o(i%i_fr3), .fr4_o(i%i_fr4), .fr5_o(i%i_fr5), .fr6_o(i%i_fr6),\n");
|
|
GEN (" .fr7_o(i%i_fr7), .fr8_o(i%i_fr8), .fr11_i(i%i_fr11i),\n ");
|
|
}
|
|
GEN (".start_i(i_start[%i]), .end_o(i_end[%i]), .busy_o(i_busy[%i]));\n", nf, nf, nf);
|
}
|
}
|
|
|
/* output footer */
|
/* output footer */
|
GEN ("\nendmodule\n");
|
GEN ("\nendmodule\n");
|
|
|
