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https://opencores.org/ocsvn/or1k/or1k/trunk
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Rev 643 |
Rev 693 |
Line 434... |
Line 434... |
int result = 0;
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int result = 0;
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unsigned long dsr = mfspr (SPR_DSR);
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unsigned long dsr = mfspr (SPR_DSR);
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unsigned long drr = mfspr (SPR_DRR);
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unsigned long drr = mfspr (SPR_DRR);
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&debug_ignore_exception;
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&debug_ignore_exception;
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printf ("0x%08x 0x%08x \n", dsr, drr);
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#if DEBUG_JTAG
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printf ("dsr 0x%08x drr 0x%08x \n", dsr, drr);
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#endif
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switch(except) {
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switch(except) {
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case EXCEPT_RESET: drr |= result = dsr & SPR_DSR_RSTE; break;
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case EXCEPT_RESET: drr |= result = dsr & SPR_DSR_RSTE; break;
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case EXCEPT_BUSERR: drr |= result = dsr & SPR_DSR_BUSEE; break;
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case EXCEPT_BUSERR: drr |= result = dsr & SPR_DSR_BUSEE; break;
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case EXCEPT_DPF: drr |= result = dsr & SPR_DSR_DPFE; break;
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case EXCEPT_DPF: drr |= result = dsr & SPR_DSR_DPFE; break;
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case EXCEPT_IPF: drr |= result = dsr & SPR_DSR_IPFE; break;
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case EXCEPT_IPF: drr |= result = dsr & SPR_DSR_IPFE; break;
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Line 452... |
Line 456... |
case EXCEPT_SYSCALL: drr |= result = dsr & SPR_DSR_SCE; break;
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case EXCEPT_SYSCALL: drr |= result = dsr & SPR_DSR_SCE; break;
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case EXCEPT_TRAP: drr |= result = dsr & SPR_DSR_TE; break;
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case EXCEPT_TRAP: drr |= result = dsr & SPR_DSR_TE; break;
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default:
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default:
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break;
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break;
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}
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}
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printf ("0x%08x 0x%08x %i\n", dsr, drr, result);
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#if DEBUG_JTAG
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printf ("dsr 0x%08x drr 0x%08x result %i\n", dsr, drr, result);
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#endif
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mtspr (SPR_DRR, drr);
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mtspr (SPR_DRR, drr);
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set_stall_state (result != 0);
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set_stall_state (result != 0);
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return (result != 0);
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return (result != 0);
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}
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}
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