| Line 65... |
Line 65... |
/* Set a specific UART register with value. */
|
/* Set a specific UART register with value. */
|
void uart_write_byte(unsigned long addr, unsigned long value)
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void uart_write_byte(unsigned long addr, unsigned long value)
|
{
|
{
|
int chipsel;
|
int chipsel;
|
|
|
debug("uart_write_byte(%x,%02x)\n", addr, (unsigned)value);
|
debug(4, "uart_write_byte(%x,%02x)\n", addr, (unsigned)value);
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|
|
for(chipsel = 0; chipsel < NR_UARTS; chipsel++)
|
for(chipsel = 0; chipsel < NR_UARTS; chipsel++)
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if ((addr & ~(UART_ADDR_SPACE-1)) == config.uarts[chipsel].baseaddr)
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if ((addr & ~(UART_ADDR_SPACE-1)) == config.uarts[chipsel].baseaddr)
|
break;
|
break;
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else if (chipsel == NR_UARTS)
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if (chipsel >= NR_UARTS) return;
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return;
|
|
|
|
if (uarts[chipsel].regs.lcr & UART_LCR_DLAB) {
|
if (uarts[chipsel].regs.lcr & UART_LCR_DLAB) {
|
switch (addr % UART_ADDR_SPACE) {
|
switch (addr % UART_ADDR_SPACE) {
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case UART_DLL:
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case UART_DLL:
|
uarts[chipsel].regs.dll = value;
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uarts[chipsel].regs.dll = value;
|
break;
|
set_char_clks(chipsel);
|
|
return;
|
case UART_DLH:
|
case UART_DLH:
|
uarts[chipsel].regs.dlh = value;
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uarts[chipsel].regs.dlh = value;
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break;
|
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case UART_LCR:
|
|
uarts[chipsel].regs.lcr = value & UART_VALID_LCR;
|
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break;
|
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default:
|
|
debug("write out of range (addr %x, DLAB=1)\n", addr);
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}
|
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set_char_clks(chipsel);
|
|
return;
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return;
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}
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}
|
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}
|
|
|
switch (addr % UART_ADDR_SPACE) {
|
switch (addr % UART_ADDR_SPACE) {
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case UART_TXBUF:
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case UART_TXBUF:
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if (uarts[chipsel].istat.txbuf_full < uarts[chipsel].fifo_len) {
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if (uarts[chipsel].istat.txbuf_full < uarts[chipsel].fifo_len) {
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uarts[chipsel].istat.txbuf_full++;
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uarts[chipsel].istat.txbuf_full++;
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| Line 121... |
Line 114... |
break;
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break;
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case UART_SCR:
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case UART_SCR:
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uarts[chipsel].regs.scr = value;
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uarts[chipsel].regs.scr = value;
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break;
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break;
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default:
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default:
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debug("write out of range (addr %x)\n", addr);
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debug(1, "write out of range (addr %x)\n", addr);
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}
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}
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set_char_clks(chipsel);
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return;
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}
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}
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|
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/* Read a specific UART register. */
|
/* Read a specific UART register. */
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unsigned long uart_read_byte(unsigned long addr)
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unsigned long uart_read_byte(unsigned long addr)
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{
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{
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unsigned char value = 0;
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unsigned char value = 0;
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int chipsel;
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int chipsel;
|
|
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debug("uart_read_byte(%x)\n", addr);
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debug(4, "uart_read_byte(%x)", addr);
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|
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for(chipsel = 0; chipsel < NR_UARTS; chipsel++)
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for(chipsel = 0; chipsel < NR_UARTS; chipsel++)
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if ((addr & ~(UART_ADDR_SPACE-1)) == config.uarts[chipsel].baseaddr)
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if ((addr & ~(UART_ADDR_SPACE-1)) == config.uarts[chipsel].baseaddr)
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break;
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break;
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else if (chipsel == NR_UARTS)
|
|
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if (chipsel >= NR_UARTS)
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return 0;
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return 0;
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|
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if (uarts[chipsel].regs.lcr & UART_LCR_DLAB) {
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if (uarts[chipsel].regs.lcr & UART_LCR_DLAB) {
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switch (addr % UART_ADDR_SPACE) {
|
switch (addr % UART_ADDR_SPACE) {
|
case UART_DLL:
|
case UART_DLL:
|
value = uarts[chipsel].regs.dll;
|
value = uarts[chipsel].regs.dll;
|
break;
|
debug(4, "= %x\n", value);
|
|
return value;
|
case UART_DLH:
|
case UART_DLH:
|
value = uarts[chipsel].regs.dlh;
|
value = uarts[chipsel].regs.dlh;
|
break;
|
debug(4, "= %x\n", value);
|
default:
|
|
debug("read out of range (addr %x, DLAB=1)\n", addr);
|
|
}
|
|
return value;
|
return value;
|
}
|
}
|
|
}
|
|
|
switch (addr % UART_ADDR_SPACE) {
|
switch (addr % UART_ADDR_SPACE) {
|
case UART_RXBUF:
|
case UART_RXBUF:
|
if (uarts[chipsel].istat.rxbuf_full) {
|
if (uarts[chipsel].istat.rxbuf_full) {
|
value = uarts[chipsel].regs.rxbuf[uarts[chipsel].istat.rxbuf_tail];
|
value = uarts[chipsel].regs.rxbuf[uarts[chipsel].istat.rxbuf_tail];
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| Line 172... |
Line 163... |
break;
|
break;
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case UART_IER:
|
case UART_IER:
|
value = uarts[chipsel].regs.ier & UART_VALID_IER;
|
value = uarts[chipsel].regs.ier & UART_VALID_IER;
|
break;
|
break;
|
case UART_IIR:
|
case UART_IIR:
|
value = uarts[chipsel].regs.iir & UART_VALID_IIR;
|
value = (uarts[chipsel].regs.iir & UART_VALID_IIR) | 0xc0;
|
uarts[chipsel].istat.thre_int = 0;
|
uarts[chipsel].istat.thre_int = 0;
|
break;
|
break;
|
case UART_LCR:
|
case UART_LCR:
|
value = uarts[chipsel].regs.lcr & UART_VALID_LCR;
|
value = uarts[chipsel].regs.lcr & UART_VALID_LCR;
|
break;
|
break;
|
case UART_MCR:
|
case UART_MCR:
|
value = uarts[chipsel].regs.mcr & UART_VALID_MCR;
|
value = 0;
|
break;
|
break;
|
case UART_LSR:
|
case UART_LSR:
|
value = uarts[chipsel].regs.lsr & UART_VALID_LSR;
|
value = uarts[chipsel].regs.lsr & UART_VALID_LSR;
|
uarts[chipsel].regs.lsr &=
|
uarts[chipsel].regs.lsr &=
|
~(UART_LSR_OVRRUN | UART_LSR_PARITY
|
~(UART_LSR_OVRRUN | UART_LSR_PARITY
|
| Line 195... |
Line 186... |
break;
|
break;
|
case UART_SCR:
|
case UART_SCR:
|
value = uarts[chipsel].regs.scr;
|
value = uarts[chipsel].regs.scr;
|
break;
|
break;
|
default:
|
default:
|
debug("read out of range (addr %x)\n", addr);
|
debug(1, "read out of range (addr %x)\n", addr);
|
}
|
}
|
|
debug(4, " = %x\n", value);
|
return value;
|
return value;
|
}
|
}
|
|
|
/* Function that handles incoming VAPI data. */
|
/* Function that handles incoming VAPI data. */
|
void uart_vapi_read (unsigned long id, unsigned long data)
|
void uart_vapi_read (unsigned long id, unsigned long data)
|
{
|
{
|
int uart;
|
int uart;
|
debug("UART: id %08x, data %08x\n", id, data);
|
debug(4, "UART: id %08x, data %08x\n", id, data);
|
uart = id & VAPI_DEVICE_ID;
|
uart = id & VAPI_DEVICE_ID;
|
uarts[uart].vapi_buf[uarts[uart].vapi_buf_head_ptr] = data;
|
uarts[uart].vapi_buf[uarts[uart].vapi_buf_head_ptr] = data;
|
uarts[uart].vapi_buf_head_ptr = (uarts[uart].vapi_buf_head_ptr + 1) % UART_RX_BUF;
|
uarts[uart].vapi_buf_head_ptr = (uarts[uart].vapi_buf_head_ptr + 1) % UART_RX_BUF;
|
if (uarts[uart].vapi_buf_tail_ptr == uarts[uart].vapi_buf_head_ptr) {
|
if (uarts[uart].vapi_buf_tail_ptr == uarts[uart].vapi_buf_head_ptr) {
|
fprintf (stderr, "FATAL: uart VAPI buffer to small.\n");
|
fprintf (stderr, "FATAL: uart VAPI buffer to small.\n");
|
| Line 258... |
Line 250... |
|
|
if (config.uarts[i].uart16550)
|
if (config.uarts[i].uart16550)
|
uarts[i].fifo_len = 16;
|
uarts[i].fifo_len = 16;
|
else
|
else
|
uarts[i].fifo_len = 1;
|
uarts[i].fifo_len = 1;
|
|
|
uarts[i].istat.rxbuf_head = uarts[i].istat.rxbuf_tail = 0;
|
uarts[i].istat.rxbuf_head = uarts[i].istat.rxbuf_tail = 0;
|
uarts[i].istat.txbuf_head = uarts[i].istat.txbuf_tail = 0;
|
uarts[i].istat.txbuf_head = uarts[i].istat.txbuf_tail = 0;
|
|
|
|
uarts[i].regs.lcr = UART_LCR_RESET;
|
}
|
}
|
}
|
}
|
|
|
/* Simulation hook. Must be called every clock cycle to simulate all UART
|
/* Simulation hook. Must be called every clock cycle to simulate all UART
|
devices. It does internal functional UART simulation. */
|
devices. It does internal functional UART simulation. */
|
| Line 289... |
Line 284... |
uarts[i].regs.lsr &= ~UART_LSR_TXSERE;
|
uarts[i].regs.lsr &= ~UART_LSR_TXSERE;
|
uarts[i].istat.thre_int = 1;
|
uarts[i].istat.thre_int = 1;
|
} else
|
} else
|
uarts[i].regs.lsr |= UART_LSR_TXSERE;
|
uarts[i].regs.lsr |= UART_LSR_TXSERE;
|
} else if (uarts[i].char_clks >= uarts[i].istat.txser_clks++) {
|
} else if (uarts[i].char_clks >= uarts[i].istat.txser_clks++) {
|
debug("TX \'%c\' via UART%d...\n", uarts[i].iregs.txser, i);
|
debug(8, "TX \'%c\' via UART%d...\n", uarts[i].iregs.txser, i);
|
if (uarts[i].regs.mcr & UART_MCR_LOOP)
|
if (uarts[i].regs.mcr & UART_MCR_LOOP)
|
uarts[i].iregs.loopback = uarts[i].iregs.txser;
|
uarts[i].iregs.loopback = uarts[i].iregs.txser;
|
else {
|
else {
|
/* Send to either VAPI or to file */
|
/* Send to either VAPI or to file */
|
if (config.uarts[i].vapi_id) {
|
if (config.uarts[i].vapi_id) {
|
| Line 308... |
Line 303... |
}
|
}
|
|
|
/* Receive */
|
/* Receive */
|
if (uarts[i].istat.rxser_full) {
|
if (uarts[i].istat.rxser_full) {
|
if (uarts[i].char_clks >= uarts[i].istat.rxser_clks++) {
|
if (uarts[i].char_clks >= uarts[i].istat.rxser_clks++) {
|
debug("Receiving via UART%d...\n", i);
|
debug(8, "Receiving via UART%d...\n", i);
|
uarts[i].istat.rxser_full = 0;
|
uarts[i].istat.rxser_full = 0;
|
uarts[i].istat.rxser_clks = 0;
|
uarts[i].istat.rxser_clks = 0;
|
|
|
if (++uarts[i].istat.rxbuf_full > uarts[i].fifo_len)
|
if (++uarts[i].istat.rxbuf_full > uarts[i].fifo_len)
|
uarts[i].regs.lsr |= UART_LSR_OVRRUN;
|
uarts[i].regs.lsr |= UART_LSR_OVRRUN;
|
| Line 343... |
Line 338... |
}
|
}
|
}
|
}
|
|
|
/* Loopback */
|
/* Loopback */
|
if (uarts[i].regs.mcr & UART_MCR_LOOP) {
|
if (uarts[i].regs.mcr & UART_MCR_LOOP) {
|
debug("uart_clock: Loopback\n");
|
debug(5, "uart_clock: Loopback\n");
|
if ((uarts[i].regs.mcr & UART_MCR_AUX2) !=
|
if ((uarts[i].regs.mcr & UART_MCR_AUX2) !=
|
((uarts[i].regs.msr & UART_MSR_DCD) >> 4))
|
((uarts[i].regs.msr & UART_MSR_DCD) >> 4))
|
uarts[i].regs.msr |= UART_MSR_DDCD;
|
uarts[i].regs.msr |= UART_MSR_DDCD;
|
if ((uarts[i].regs.mcr & UART_MCR_AUX1) <
|
if ((uarts[i].regs.mcr & UART_MCR_AUX1) <
|
((uarts[i].regs.msr & UART_MSR_RI) >> 4))
|
((uarts[i].regs.msr & UART_MSR_RI) >> 4))
|
| Line 417... |
Line 412... |
printf("\nInternal status (sim debug):\n");
|
printf("\nInternal status (sim debug):\n");
|
printf("char_clks: %d\n", uarts[i].char_clks);
|
printf("char_clks: %d\n", uarts[i].char_clks);
|
printf("rxser_clks: %d txser_clks: %d\n", uarts[i].istat.rxser_clks, uarts[i].istat.txser_clks);
|
printf("rxser_clks: %d txser_clks: %d\n", uarts[i].istat.rxser_clks, uarts[i].istat.txser_clks);
|
printf("rxser: %d txser: %d\n", uarts[i].istat.rxser_full, uarts[i].istat.txser_full);
|
printf("rxser: %d txser: %d\n", uarts[i].istat.rxser_full, uarts[i].istat.txser_full);
|
printf("rxbuf: %d txbuf: %d\n", uarts[i].istat.rxbuf_full, uarts[i].istat.txbuf_full);
|
printf("rxbuf: %d txbuf: %d\n", uarts[i].istat.rxbuf_full, uarts[i].istat.txbuf_full);
|
printf("Using IRQ%i", config.uarts[i].irq);
|
printf("Using IRQ%i\n", config.uarts[i].irq);
|
if (config.uarts[i].vapi_id)
|
if (config.uarts[i].vapi_id)
|
printf ("Connected to vapi ID=%x\n\n", config.uarts[i].vapi_id);
|
printf ("Connected to vapi ID=%x\n\n", config.uarts[i].vapi_id);
|
else
|
else
|
printf("RX fs: %p TX fs: %p\n\n", uarts[i].rxfs, uarts[i].txfs);
|
printf("RX fs: %p TX fs: %p\n\n", uarts[i].rxfs, uarts[i].txfs);
|
}
|
}
|
