| Line 120... |
Line 120... |
}
|
}
|
break;
|
break;
|
case UART_IER:
|
case UART_IER:
|
uarts[chipsel].regs.ier = value & UART_VALID_IER;
|
uarts[chipsel].regs.ier = value & UART_VALID_IER;
|
#if 0
|
#if 0
|
|
if (uarts[chipsel].regs.ier & UART_IER_THRI)
|
uarts[chipsel].istat.thre_int = 1;
|
uarts[chipsel].istat.thre_int = 1;
|
#endif
|
#endif
|
break;
|
break;
|
case UART_LCR:
|
case UART_LCR:
|
uarts[chipsel].regs.lcr = value & UART_VALID_LCR;
|
uarts[chipsel].regs.lcr = value & UART_VALID_LCR;
|
| Line 194... |
Line 195... |
case UART_IER:
|
case UART_IER:
|
value = uarts[chipsel].regs.ier & UART_VALID_IER;
|
value = uarts[chipsel].regs.ier & UART_VALID_IER;
|
break;
|
break;
|
case UART_IIR:
|
case UART_IIR:
|
value = (uarts[chipsel].regs.iir & UART_VALID_IIR) | 0xc0;
|
value = (uarts[chipsel].regs.iir & UART_VALID_IIR) | 0xc0;
|
if (uarts[chipsel].regs.iir & UART_IER_THRI)
|
if (uarts[chipsel].regs.ier & UART_IER_THRI)
|
uarts[chipsel].istat.thre_int = 0;
|
uarts[chipsel].istat.thre_int = 0;
|
break;
|
break;
|
case UART_LCR:
|
case UART_LCR:
|
value = uarts[chipsel].regs.lcr & UART_VALID_LCR;
|
value = uarts[chipsel].regs.lcr & UART_VALID_LCR;
|
break;
|
break;
|
| Line 378... |
Line 379... |
uarts[i].istat.rxbuf_head = uarts[i].istat.rxbuf_tail = 0;
|
uarts[i].istat.rxbuf_head = uarts[i].istat.rxbuf_tail = 0;
|
uarts[i].istat.txbuf_head = uarts[i].istat.txbuf_tail = 0;
|
uarts[i].istat.txbuf_head = uarts[i].istat.txbuf_tail = 0;
|
|
|
uarts[i].istat.break_set = 0;
|
uarts[i].istat.break_set = 0;
|
uarts[i].istat.timeout_count = 0;
|
uarts[i].istat.timeout_count = 0;
|
uarts[i].istat.thre_int = 0;
|
uarts[i].istat.thre_int = 1; /* FIFO is empty at start */
|
|
|
uarts[i].regs.lcr = UART_LCR_RESET;
|
uarts[i].regs.lcr = UART_LCR_RESET;
|
uarts[i].vapi.cur_break = uarts[i].vapi.cur_break_cnt = uarts[i].vapi.next_break = 0;
|
uarts[i].vapi.cur_break = uarts[i].vapi.cur_break_cnt = uarts[i].vapi.next_break = 0;
|
uarts[i].vapi.next_break_cnt = -1;
|
uarts[i].vapi.next_break_cnt = -1;
|
}
|
}
|
