| Line 56... |
Line 56... |
{
|
{
|
unsigned i;
|
unsigned i;
|
|
|
memset( dmas, 0, sizeof(dmas) );
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memset( dmas, 0, sizeof(dmas) );
|
|
|
for ( i = 0; i < NR_DMAS; ++ i ) {
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if (!config.dmas_enabled)
|
|
config.ndmas = 0;
|
|
|
|
for ( i = 0; i < config.ndmas; ++ i ) {
|
struct dma_controller *dma = &(dmas[i]);
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struct dma_controller *dma = &(dmas[i]);
|
unsigned channel_number;
|
unsigned channel_number;
|
|
|
dma->baseaddr = config.dmas[i].baseaddr;
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dma->baseaddr = config.dmas[i].baseaddr;
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dma->irq = config.dmas[i].irq;
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dma->irq = config.dmas[i].irq;
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| Line 69... |
Line 72... |
dma->ch[channel_number].channel_number = channel_number;
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dma->ch[channel_number].channel_number = channel_number;
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dma->ch[channel_number].channel_mask = 1LU << channel_number;
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dma->ch[channel_number].channel_mask = 1LU << channel_number;
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dma->ch[channel_number].regs.am0 = dma->ch[channel_number].regs.am1 = 0xFFFFFFFC;
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dma->ch[channel_number].regs.am0 = dma->ch[channel_number].regs.am1 = 0xFFFFFFFC;
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}
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}
|
if ( dma->baseaddr != 0 )
|
if ( dma->baseaddr != 0 )
|
register_memoryarea( dma->baseaddr, DMA_ADDR_SPACE, 4, dma_read32, dma_write32, 0 );
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register_memoryarea( dma->baseaddr, DMA_ADDR_SPACE, 4, dma_read32, dma_write32);
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}
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}
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}
|
}
|
|
|
/* Print register values on stdout */
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/* Print register values on stdout */
|
void dma_status( void )
|
void dma_status( void )
|
{
|
{
|
unsigned i, j;
|
unsigned i, j;
|
|
|
for ( i = 0; i < NR_DMAS; ++ i ) {
|
for ( i = 0; i < config.ndmas; ++ i ) {
|
struct dma_controller *dma = &(dmas[i]);
|
struct dma_controller *dma = &(dmas[i]);
|
|
|
if ( dma->baseaddr == 0 )
|
if ( dma->baseaddr == 0 )
|
continue;
|
continue;
|
|
|
