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This directory includes some test case programs that should be used to verify correct operation
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This directory includes some test case programs that should be used to verify correct operation
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of the or1ksim, OR32 GCC and OR32 GNU Binutils.
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of the or1ksim, OR32 GCC and OR32 GNU Binutils.
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All programs should be built inside their directories (ie. dhrystone should be built
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All programs are built from root directories. You need to have all GNU OR32 tools installed and in
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inside testbench/dhrystone). You need to have all GNU OR32 tools installed and in path.
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path.
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All makefiles assume or32-rtems target.
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!!! For all test cases, or1ksim should be built with ONLY_VIRTUAL_MACHINE undefined in
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!!! For all test cases, or1ksim should be built with ONLY_VIRTUAL_MACHINE undefined in
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cpu/or1k/except.h !!!
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cpu/or1k/except.h !!!
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Dhrystone 2.1: a benchmark modified to use simulator's timing facility. It should finish with exit(0).
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Dhrystone 2.1: a benchmark modified to use simulator's timing facility. It should finish with exit(0).
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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running simulation:
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running simulation:
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# ./sim testbench/dhrystone/dhry.or32
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# ./sim testbench/dhrystone/dhry.or32
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(sim) run 1000000 hush
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(sim) run -1 hush
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MTSPR(0x1234, 20070);
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MTSPR(0x1234, 20070);
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MTSPR(0x1234, 20013);
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MTSPR(0x1234, 20013);
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MTSPR(0x1234, 7);
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MTSPR(0x1234, 7);
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MTSPR(0x1234, 30010);
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MTSPR(0x1234, 30010);
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End Time = 22701
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End Time = 22701
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OR1K at 200 MHz
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OR1K at 200 MHz
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Microseconds for one run through Dhrystone: 110 us / 20 runs
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Microseconds for one run through Dhrystone: 110 us / 20 runs
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Dhrystones per Second: 181
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Dhrystones per Second: 181
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test0: a test for all instructions and all GPRs. If everything is ok, RESULT == 0xdeadead.
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basic: a test for all instructions and all GPRs. If everything is ok, RESULT == 0xdeadead.
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Simulation:
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Simulation:
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# ./sim testbench/test0/test0.or32
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# ./sim testbench/basic.or32
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(sim) run 1000000000 hush
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(sim) run -1 hush
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UART 0 RX EOF detected. Shutting down to prevent endless loop.
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UART 0 RX EOF detected. Shutting down to prevent endless loop.
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MTSPR(0x1234, ffff0012);
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MTSPR(0x1234, ffff0012);
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MTSPR(0x1234, 12352af7);
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MTSPR(0x1234, 12352af7);
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MTSPR(0x1234, 7ffffffe);
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MTSPR(0x1234, 7ffffffe);
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MTSPR(0x1234, ffffa5a7);
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MTSPR(0x1234, ffffa5a7);
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test1: a test for "all" instructions and their combinations. If everything is ok, RESULT == 0xdeadead.
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test1: a test for "all" instructions and their combinations. If everything is ok, RESULT == 0xdeadead.
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Simulation:
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Simulation:
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# ./sim testbench/test1/test1.or32
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# ./sim testbench/cbasic.or32
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(sim) run 100000000 hush
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(sim) run -1 hush
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MTSPR(0x1234, ffffffda);
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MTSPR(0x1234, ffffffda);
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MTSPR(0x1234, ffffffc5);
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MTSPR(0x1234, ffffffc5);
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MTSPR(0x1234, 6805);
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MTSPR(0x1234, 6805);
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MTSPR(0x1234, ffff97f9);
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MTSPR(0x1234, ffff97f9);
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MTSPR(0x1234, ffff97f9);
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MTSPR(0x1234, ffff97f9);
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(sim)
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(sim)
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Standard output:
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Standard output:
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RESULT: deaddead
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RESULT: deaddead
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test2: a test for PIC and TICK timer. All three modes of TICK timer are tested and interrupt is enabled and disabled in PIC. If everything is ok, RESULT == 0xdeadead.
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pic: a test for PIC and TICK timer. All three modes of TICK timer are tested and interrupt is enabled and disabled in PIC. If everything is ok, RESULT == 0xdeadead.
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Simulation:
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Simulation:
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# ./sim testbench/test2/test2.or32
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# ./sim testbench/pic.or32
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(sim) run 100000000 hush
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(sim) run -1 hush
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...
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...
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...
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...
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...
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...
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MTSPR(0x1234, 178);
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MTSPR(0x1234, 178);
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MTSPR(0x1234, 178);
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MTSPR(0x1234, 178);
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(sim)
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(sim)
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Standard output:
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Standard output:
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RESULT: deaddead
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RESULT: deaddead
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test3: a test of l.sys instruction. Checks all the delay slot issues ind other things. If everything is ok, RESULT == 0xdeadead.
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excpt: a test of l.sys instruction. Checks all the delay slot issues ind other things. If everything is ok, RESULT == 0xdeadead.
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Simulation:
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Simulation:
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# ./sim testbench/test3/test3.or32
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# ./sim testbench/excpt.or32
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(sim) run 1000000 hush
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(sim) run -1 hush
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UART 0 RX EOF detected. Shutting down to prevent endless loop.
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UART 0 RX EOF detected. Shutting down to prevent endless loop.
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Exception 0xc00 (System Call): Iqueue[0].insn_addr: 0xc74 Eff ADDR: 0x0
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Exception 0xc00 (System Call): Iqueue[0].insn_addr: 0xc74 Eff ADDR: 0x0
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pc: 0xc74 pcnext: 0xc78
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pc: 0xc74 pcnext: 0xc78
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MTSPR(0x1234, 1);
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MTSPR(0x1234, 1);
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MTSPR(0x1234, 1);
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MTSPR(0x1234, 1);
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(sim)
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(sim)
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Standard output:
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Standard output:
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RESULT: deaddead
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RESULT: deaddead
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test4: a test of SPRs (SPR_VR, SPR_CPUCFGR, SPR_DMMUCFGR, SPR_IMMUCFGR, SPR_DCCFGR, SPR_ICCFGR, SPR_DCFGR, SPR_PCCFGR). If everything is ok, RESULT == 0xdeadead.
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cfg: a test of SPRs (SPR_VR, SPR_CPUCFGR, SPR_DMMUCFGR, SPR_IMMUCFGR, SPR_DCCFGR, SPR_ICCFGR, SPR_DCFGR, SPR_PCCFGR). If everything is ok, RESULT == 0xdeadead.
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Simulation:
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Simulation:
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# ./sim testbench/test4/test4.or32
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# ./sim testbench/cfg.or32
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(sim) run 1000000 hush
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(sim) run -1 hush
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MTSPR(0x1234, 0);
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MTSPR(0x1234, 0);
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MTSPR(0x1234, e83f);
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MTSPR(0x1234, e83f);
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MTSPR(0x1234, 0);
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MTSPR(0x1234, 0);
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MTSPR(0x1234, 5);
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MTSPR(0x1234, 5);
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MTSPR(0x1234, 20);
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MTSPR(0x1234, 20);
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(sim)
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(sim)
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Standard output:
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Standard output:
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RESULT: deaddead
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RESULT: deaddead
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test5: a test of DMA in normal (software) mode. If everything is ok, RESULT == 0xdeadead.
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dma: a test of DMA in normal (software) mode. If everything is ok, RESULT == 0xdeadead.
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Simulation:
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Simulation:
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# ./sim testbench/test5/test5.or32
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# ./sim testbench/dma.or32
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(sim) run 1000000 hush
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(sim) run 1000000 hush
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MTSPR(0x1234, 1);
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MTSPR(0x1234, 1);
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MTSPR(0x1234, 6);
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MTSPR(0x1234, 6);
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MTSPR(0x1234, a);
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MTSPR(0x1234, a);
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MTSPR(0x1234, deaddead);
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MTSPR(0x1234, deaddead);
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Simulation:
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Simulation:
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./sim testbench/compress/mycompress.or32
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./sim testbench/compress/mycompress.or32
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(sim) run 100000000 hush
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(sim) run -1 hush
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Interrupt reported.
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Interrupt reported.
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Interrupt reported.
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Interrupt reported.
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syscall exit(0)
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syscall exit(0)
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(sim)
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(sim)
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main: compressing 998...
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main: compressing 998...
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main: compressing 999...
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main: compressing 999...
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main: output...
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main: output...
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main: end...
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main: end...
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mul: Test l.mul, l.mac and l.macrc instructions. Should finish with exit(0).
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Simulation:
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./sim testbench/mul.or32
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(sim) run -1 hush
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MTSPR(0x1234, deadbeef);
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syscall exit(0)
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(sim)
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Standard output:
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0xa6312f33, expected 0xa6312f33
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0x0d4de375, expected 0x0d4de375
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0x61ab48dc, expected 0x61ab48dc
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Test succesful.
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