URL https://opencores.org/ocsvn/or1k/or1k/trunk

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[/] [or1k/] [tags/] [nog_patch_47/] [or1ksim/] [testbench/] [acv_gpio.c] - Diff between revs 483 and 499

Rev 483	Rev 499
Line 1...	Line 1...
`/* GPIO test */`	`/* GPIO test */`

`#include "spr_defs.h"`	`#include "spr_defs.h"`
`#include "support.h"`	`#include "support.h"`
	`#include "int.h"`

`/* Relative Register Addresses */`	`/* Relative Register Addresses */`
`#define RGPIO_IN (4 * 0x00)`	`#define RGPIO_IN (4 * 0x00)`
`#define RGPIO_OUT (4 * 0x01)`	`#define RGPIO_OUT (4 * 0x01)`
`#define RGPIO_OE (4 * 0x02)`	`#define RGPIO_OE (4 * 0x02)`
Line 59...	Line 60...
`}`	`}`
`}`	`}`

`static volatile unsigned int_count = 0;`	`static volatile unsigned int_count = 0;`

`static void interrupt_handler( void )`
	`static void gpio_interrupt( void *arg )`
`{`	`{`
`++ int_count;`	`++ int_count;`
`mtspr( SPR_PICSR, 0 );`
`}`	`}`

`static void init_interrupts( void )`	`static void init_interrupts( void )`
`{`	`{`
`/* Use our low priority interrupt handler */`	`int_init();`
`excpt_lpint = (unsigned long)interrupt_handler;`	`int_add( GPIO_INT_LINE, gpio_interrupt, 0, INT_LOW_PRI );`

`/* Enable interrupts */`	`/* Enable interrupts */`
`mtspr( SPR_SR, mfspr(SPR_SR) \| SPR_SR_EXR \| SPR_SR_EIR );`	`mtspr( SPR_SR, mfspr(SPR_SR) \| SPR_SR_EXR \| SPR_SR_EIR );`
`mtspr( SPR_PICMR, mfspr(SPR_PICMR) \| (0x00000001L << GPIO_INT_LINE) );`
`}`	`}`



`static void test_registers( void )`	`static void test_registers( void )`